| 2018 | ASPDAC | Clustering of flip-flops for useful-skew clock tree synthesis. | Chuan Yean Tan, Rickard Ewetz, Cheng-Kok Koh |
| 2017 | ASPDAC | Delay-driven layer assignment for advanced technology nodes. | Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang |
| 2017 | CoNEXT | Saath: Speeding up CoFlows by Exploiting the Spatial Dimension. | Akshay Jajoo, Rohan Gandhi, Y. Charlie Hu, Cheng-Kok Koh |
| 2016 | ASPDAC | MCMM clock tree optimization based on slack redistribution using a reduced slack graph. | Rickard Ewetz, Cheng-Kok Koh |
| 2015 | ASPDAC | Fast clock skew scheduling based on sparse-graph algorithms. | Rickard Ewetz, Shankarshana Janarthanan, Cheng-Kok Koh |
| 2015 | DAC | Construction of reconfigurable clock trees for MCMM designs. | Rickard Ewetz, Shankarshana Janarthanan, Cheng-Kok Koh |
| 2015 | IROS | Human-pose estimation with neural-network realization. | Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee |
| 2015 | USENIX | Rubik: Unlocking the Power of Locality and End-point Flexibility in Cloud Scale Load Balancing. | Rohan Gandhi, Y. Charlie Hu, Cheng-Kok Koh, Hongqiang Harry Liu, Ming Zhang |
| 2014 | ASPDAC | Analytical placement of mixed-size circuits for better detailed-routability. | Shuai Li, Cheng-Kok Koh |
| 2014 | ICRA | Selecting best viewpoint for human-pose estimation. | Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee |
| 2013 | DAC | Optimization of placement solutions for routability. | Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li |
| 2013 | ICRA | A 3D-point-cloud feature for human-pose estimation. | Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee |
| 2013 | IROS | Using action classification for human-pose estimation. | Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee |
| 2012 | ICCAD | A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing. | Wen-Hao Liu, Yih-Lang Li, Cheng-Kok Koh |
| 2011 | ASPDAC | Simultaneous redundant via insertion and line end extension for yield optimization. | Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao |
| 2011 | ISLPED | Processor caches with multi-level spin-transfer torque ram cells. | Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh |
| 2010 | ICCAD | PEDS: Passivity enforcement for descriptor systems via Hamiltonian-symplectic matrix pencil perturbation. | Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Grantham K. H. Pang, Ngai Wong |
| 2009 | DAC | A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction. | Wenwen Chai, Dan Jiao, Cheng-Kok Koh |
| 2009 | ICCAD | A study of routability estimation and clustering in placement. | Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan |
| 2009 | ICCD | The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies. | Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li |
| 2008 | ICCAD | Guiding global placement with wire density. | Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan |
| 2008 | ISCAS | A fast band matching technique for impedance extraction. | Jitesh Jain, Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan |
| 2007 | ICCAD | A fast band-matching technique for interconnect inductance modeling. | Hong Li, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan |
| 2007 | ICCAD | A frequency-domain technique for statistical timing analysis of clock meshes. | Ruilin Wang, Cheng-Kok Koh |
| 2007 | ICCD | VOSCH: Voltage scaled cache hierarchies. | Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li |
| 2007 | ISLPED | Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. | Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh |
| 2006 | ASPDAC | SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices. | Jitesh Jain, Stephen Cauley, Cheng-Kok Koh, Venkataramanan Balakrishnan |
| 2006 | ASPDAC | SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. | Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh |
| 2006 | ASPDAC | Adaptive admittance-based conductor meshing for interconnect analysis. | Ya-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan |
| 2006 | ICCAD | Stable and compact inductance modeling of 3-D interconnect structures. | Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh |
| 2005 | ASPDAC | Post-layout logic duplication for synthesis of domino circuits with complex gates. | Aiqun Cao, Ruibing Lu, Cheng-Kok Koh |
| 2005 | ASPDAC | Process variation robust clock tree routing. | Wai-Ching Douglas Lam, Cheng-Kok Koh |
| 2005 | ASPDAC | Compact and stable modeling of partial inductance and reluctance matrices. | Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh, Guoan Zhong |
| 2005 | ASPDAC | Floorplan management: incremental placement for gate sizing and buffer insertion. | Chen Li, Cheng-Kok Koh, Patrick H. Madden |
| 2005 | ASPDAC | Improving the scalability of SAMBA bus architecture. | Ruibing Lu, Aiqun Cao, Cheng-Kok Koh |
| 2005 | ICCAD | Statistical based link insertion for robust clock network design. | Wai-Ching Douglas Lam, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen |
| 2005 | ISLPED | Cascaded carry-select adder (C | Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh |
| 2004 | ASPDAC | Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. | Yiran Chen, Kaushik Roy, Cheng-Kok Koh |
| 2004 | ASPDAC | A high performance bus communication architecture through bus splitting. | Ruibing Lu, Cheng-Kok Koh |
| 2004 | DAC | Post-layout logic optimization of domino circuits. | Aiqun Cao, Cheng-Kok Koh |
| 2004 | DAC | Passivity-preserving model reduction via a computationally efficient project-and-balance scheme. | Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh |
| 2004 | ICASSP | A fast Newton/Smith algorithm for solving algebraic Riccati equations and its application in model order reduction. | Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh, Tung-Sang Ng |
| 2004 | ICCAD | Fast simulation of VLSI interconnects. | Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan |
| 2004 | ICCAD | Routability-driven placement and white space allocation. | Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden |
| 2003 | ASPDAC | Integer linear programming-based synthesis of skewed logic circuits. | Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy |
| 2003 | ASPDAC | A metric for analyzing effective on-chip inductive coupling. | Guoan Zhong, Cheng-Kok Koh, Kaushik Roy |
| 2003 | DAC | An adaptive window-based susceptance extraction and its efficient implementation. | Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy |
| 2003 | DATE | Interconnect Planning with Local Area Constrained Retiming. | Ruibing Lu, Cheng-Kok Koh |
| 2003 | ICCAD | SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. | Ruibing Lu, Cheng-Kok Koh |
| 2003 | ICCAD | Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels. | Ruibing Lu, Cheng-Kok Koh |
| 2003 | ICCD | Non-Crossing OBDDs for Mapping to Regular Circuit Structures. | Aiqun Cao, Cheng-Kok Koh |
| 2003 | ISLPED | Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. | Yiran Chen, Kaushik Roy, Cheng-Kok Koh |
| 2002 | DAC | A factorization-based framework for passivity-preserving model reduction of RLC systems. | Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh |
| 2002 | DATE | Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. | Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy |
| 2002 | DATE | Flip-Flop and Repeater Insertion for Early Interconnect Planning. | Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao |
| 2002 | ICCAD | On-chip interconnect modeling by wire duplication. | Guoan Zhong, Cheng-Kok Koh, Kaushik Roy |
| 2002 | ICCD | Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects. | Guoan Zhong, Cheng-Kok Koh |
| 2002 | VLSID | Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods. | Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh |
| 2002 | VLSID | Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. | Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh |
| 2001 | DAC | Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. | Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes |
| 2001 | DATE | Repeater block planning under simultaneous delay and transition time constraints. | Probir Sarkar, Cheng-Kok Koh |
| 2001 | ISCAS | Short-circuit power analysis of an inverter driving an RLC load. | Rui Wang, Kaushik Roy, Cheng-Kok Koh |
| 2001 | ISCAS | Power trends and performance characterization of 3-dimensional integration. | Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes |
| 2001 | ISLPED | Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. | Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy |
| 2000 | ICCAD | UST/DME: A Clock Tree Router for General Skew Constraints. | Chung-Wen Albert Tsao, Cheng-Kok Koh |
| 2000 | ICCAD | Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. | Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes |
| 2000 | ICCAD | Frequency Domain Analysis of Switching Noise on Power Supply Network. | Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh |
| 2000 | ICCAD | A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. | Guoan Zhong, Cheng-Kok Koh, Kaushik Roy |
| 2000 | ICCD | Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. | Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar |
| 2000 | ICCD | Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. | Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh |
| 1997 | ICCAD | Global interconnect sizing and spacing with consideration of coupling capacitance. | Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan |
| 1997 | ICCAD | Interconnect layout optimization under higher-order RLC model. | Jason Cong, Cheng-Kok Koh |
| 1997 | ICCAD | Interconnect design for deep submicron ICs. | Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo |
| 1996 | ISLPED | Simultaneous buffer and wire sizing for performance and power optimization. | Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung |
| 1995 | ICCAD | Bounded-skew clock and Steiner routing under Elmore delay. | Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao |
| 1995 | ISCAS | Minimum-Cost Bounded-Skew Clock Routing. | Jason Cong, Cheng-Kok Koh |
| 1994 | ICCAD | Simultaneous driver and wire sizing for performance and power optimization. | Jason Cong, Cheng-Kok Koh |