| 2026 | FPGA | vFPGA: Towards Sub-s Reconfiguration via 3D FPGA and Packaging Co-Design. | Nikhil K. Cherukuri, Sharad Nag, Pragnya Sudershan Nalla, Ashish K. Kola, Chetan S. Gadireddi, Kevin Dai, Jae-sun Seo, Zhenman Fang, Jeff Zhang, Yu Cao |
| 2026 | ICPR | SAVAF: Sparse Audio-Visual Rendering with Multihead Acoustic Field Attention Network. | Ahmed Hasssan, Jian Meng, Sungjin Park, Jae-sun Seo |
| 2026 | ISCAS | A 22nm Reconfigurable Systolic Array for FFT and AI Inference. | John Stolzberg-Schray, Sharad Nag, Jacob Johnson, Nikhil K. Cherukuri, Ashish K. Kola, Gopikrishnan Raveendran Nair, Jeff Zhang, Jae-sun Seo, Yu Kevin Cao |
| 2026 | WACV | DCSHARP: 3D Gaussian Splatting with Direction Cosine Spherical Harmonics and Shape-Aware Pruning. | Ahmed Hasssan, Jian Meng, Yuanbo Xiangli, Jae-sun Seo |
| 2025 | CVPR | Closest Neighbors are Harmful for Lightweight Masked Auto-encoders. | Jian Meng, Ahmed Hassan, Li Yang, Deliang Fan, Jinwoo Shin, Jae-sun Seo |
| 2025 | ICASSP | Quant-NeRF: Efficient End-to-End Quantization of Neural Radiance Fields with Low-Precision 3D Gaussian Representation. | Ahmed Hasssan, Anupreetham Anupreetham, Jian Meng, Jae-sun Seo |
| 2025 | ICML | Skrr: Skip and Re-use Text Encoder Layers for Memory Efficient Text-to-Image Generation. | Hoigi Seo, Wongi Jeong, Jae-sun Seo, Se Young Chun |
| 2025 | ISLPED | Hybrid Systolic Array Accelerator with Optimized Dataflow for Edge Large Language Model Inference. | Chun-Ting Chen, HanGyeol Mun, Jian Meng, Mohamed S. Abdelfattah, Jae-sun Seo |
| 2024 | ECCV | POCA: Post-training Quantization with Temporal Alignment for Codec Avatars. | Jian Meng, Yuecheng Li, Chenghui Li, Syed Shakib Sarwar, Dilin Wang, Jae-sun Seo |
| 2024 | ISLPED | 3D IC Architecture Evaluation and Optimization with Digital Compute-in-Memory Designs. | Hyung Joon Byun, Udit Gupta, Jae-sun Seo |
| 2024 | ISLPED | A 28nm Scalable and Flexible Accelerator for Sparse Transformer Models. | Yuan Liao, Jian Meng, Jae-sun Seo |
| 2024 | MICRO | BBS: Bi-Directional Bit-Level Sparsity for Deep Learning Acceleration. | Yuzong Chen, Jian Meng, Jae-sun Seo, Mohamed S. Abdelfattah |
| 2023 | DATE | PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration. | Wangxin He, Jian Meng, Sujan Kumar Gonugondla, Shimeng Yu, Naresh R. Shanbhag, Jae-sun Seo |
| 2023 | DATE | FPGA Acceleration of GCN in Light of the Symmetry of Graph Adjacency Matrix. | Gopikrishnan Raveendran Nair, Han-Sok Suh, Mahantesh Halappanavar, Frank Liu, Jae-sun Seo, Yu Cao |
| 2023 | ISCAS | Improving the Efficiency of CMOS Image Sensors through In-Sensor Selective Attention. | Tianyi Zhang, Kishore Kasichainula, Dong-Woo Jee, Injune Yeo, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, Yu Cao |
| 2022 | ACSSC | Spatial-temporal Data Compression of Dynamic Vision Sensor Output with High Pixel-level Saliency using Low-precision Sparse Autoencoder. | Ahmed Hassan, Jian Meng, Yu Cao, Jae-sun Seo |
| 2022 | ASPDAC | XBM: A Crossbar Column-wise Binary Mask Learning Method for Efficient Multiple Task Adaption. | Fan Zhang, Li Yang, Jian Meng, Yu Kevin Cao, Jae-sun Seo, Deliang Fan |
| 2022 | DAC | XMA: a crossbar-aware multi-task adaption framework via shift-based mask learning method. | Fan Zhang, Li Yang, Jian Meng, Jae-sun Seo, Yu Kevin Cao, Deliang Fan |
| 2022 | ICCAD | Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture. | Gokul Krishnan, A. Alper Goksoy, Sumit K. Mandal, Zhenyu Wang, Chaitali Chakrabarti, Jae-sun Seo, mit Y. Ogras, Yu Cao |
| 2021 | DAC | Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks. | Sai Kiran Cherupally, Adnan Siraj Rakin, Shihui Yin, Mingoo Seok, Deliang Fan, Jae-sun Seo |
| 2021 | FPL | End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. | Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo |
| 2021 | FPL | FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access. | Jian Meng, Shreyas Kolala Venkataramanaiah, Chuteng Zhou, Patrick Hansen, Paul N. Whatmough, Jae-sun Seo |
| 2021 | ISCAS | Hybrid In-Memory Computing Architecture for the Training of Deep Neural Networks. | Vinay Joshi, Wangxin He, Jae-sun Seo, Bipin Rajendran |
| 2020 | CVPR | Noise-based Selection of Robust Inherited Model for Accurate Continual Learning. | Xiaocong Du, Zheng Li, Jae-sun Seo, Frank Liu, Yu Cao |
| 2020 | DATE | An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays. | Shruti R. Kulkarni, Shihui Yin, Jae-sun Seo, Bipin Rajendran |
| 2020 | IJCAI | Efficient and Modularized Training on FPGA for Real-time Applications. | Shreyas Kolala Venkataramanaiah, Xiaocong Du, Zheng Li, Shihui Yin, Yu Cao, Jae-sun Seo |
| 2020 | IJCNN | Online Knowledge Acquisition with the Selective Inherited Model. | Xiaocong Du, Shreyas Kolala Venkataramanaiah, Zheng Li, Jae-sun Seo, Frank Liu, Yu Cao |
| 2020 | Interspeech | Compressing LSTM Networks with Hierarchical Coarse-Grain Sparsity. | Deepak Kadetotad, Jian Meng, Visar Berisha, Chaitali Chakrabarti, Jae-sun Seo |
| 2019 | ACSSC | Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration. | Zhewei Jiang, Shihui Yin, Minkyu Kim, Tushar Gupta, Mingoo Seok, Jae-sun Seo |
| 2019 | FPL | Automatic Compiler Based FPGA Accelerator for CNN Training. | Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo |
| 2019 | ICASSP | Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks. | Gaurav Srivastava, Deepak Kadetotad, Shihui Yin, Visar Berisha, Chaitali Chakrabarti, Jae-sun Seo |
| 2019 | ISCAS | ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression. | Sai Kiran Cherupally, Gaurav Srivastava, Shihui Yin, Deepak Kadetotad, Chisung Bae, Sang Joon Kim, Jae-sun Seo |
| 2019 | ISLPED | K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM. | Jyotishman Saikia, Shihui Yin, Zhewei Jiang, Mingoo Seok, Jae-sun Seo |
| 2018 | ASPDAC | Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. | Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu |
| 2018 | DATE | XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. | Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu |
| 2018 | ICASSP | Towards a Wearable Cough Detector Based on Neural Networks. | Prad Kadambi, Abinash Mohanty, Hao Ren, Jaclyn Smith, Kevin McGuinnes, Kimberly Holt, Armin Furtwaengler, Roberto Slepetys, Zheng Yang, Jae-sun Seo, Junseok Chae, Yu Cao, Visar Berisha |
| 2018 | ICCAD | Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs. | Yufei Ma, Tu Zheng, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo |
| 2017 | ACSSC | Minimizing area and energy of deep learning hardware design using collective low precision and structured compression. | Shihui Yin, Gaurav Srivastava, Shreyas K. Venkataramanaiah, Chaitali Chakrabarti, Visar Berisha, Jae-sun Seo |
| 2017 | ASPDAC | A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. | Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo |
| 2017 | ASPDAC | Low-power neuromorphic speech recognition engine with coarse-grain sparsity. | Shunti Yin, Deepak Kadetotad, Bonan Yan, Chang Song, Yiran Chen, Chaitali Chakrabarti, Jae-sun Seo |
| 2017 | DATE | Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators. | Xiaoyang Mi, Hesam Fathi Moghadam, Jae-sun Seo |
| 2017 | FPGA | Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. | Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo |
| 2017 | FPL | An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. | Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo |
| 2017 | ISCAS | A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. | Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo |
| 2017 | ISCAS | End-to-end scalable FPGA accelerator for deep residual networks. | Yufei Ma, Minkyu Kim, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo |
| 2017 | ISLPED | Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition. | Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, Sung Kyu Lim |
| 2017 | IWANN | Comprehensive Evaluation of OpenCL-Based CNN Implementations for FPGAs. | Ricardo Tapiador-Morales, Antonio Rios-Navarro, Alejandro Linares-Barranco, Minkyu Kim, Deepak Kadetotad, Jae-sun Seo |
| 2016 | FPGA | Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. | Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao |
| 2016 | FPL | Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. | Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula |
| 2016 | ICASSP | Ranking the parameters of deep neural networks using the fisher information. | Ming Tu, Visar Berisha, Martin Woolf, Jae-sun Seo, Yu Cao |
| 2016 | ICCAD | Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing. | Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu |
| 2016 | ICCAD | Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications. | Deepak Kadetotad, Sairam Arunachalam, Chaitali Chakrabarti, Jae-sun Seo |
| 2016 | ICDM | Bi-Level Rare Temporal Pattern Detection. | Dawei Zhou, Jingrui He, Yu Cao, Jae-sun Seo |
| 2016 | ISCAS | High-performance face detection with CPU-FPGA acceleration. | Abinash Mohanty, Naveen Suda, Minkyu Kim, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao |
| 2015 | DATE | Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. | Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu |
| 2015 | ICCAD | Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. | Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu |
| 2015 | ICCD | Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits. | Yufei Ma, Minkyu Kim, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula |
| 2015 | ISLPED | Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS. | Xiaoyang Mi, Debashis Mandal, Visvesh S. Sathe, Bertan Bakkaloglu, Jae-sun Seo |
| 2015 | ISLPED | Analysis and optimization of CMOS switched-capacitor converters. | Visvesh S. Sathe, Jae-sun Seo |
| 2015 | ISLPED | A neuromorphic neural spike clustering processor for deep-brain sensing and stimulation systems. | Beinuo Zhang, Zhewei Jiang, Qi Wang, Jae-sun Seo, Mingoo Seok |
| 2008 | ICCAD | On the decreasing significance of large standard cells in technology mapping. | Jae-sun Seo, Igor L. Markov, Dennis Sylvester, David T. Blaauw |
| 2008 | ISCAS | A robust alternate repeater technique for high performance busses in the multi-core era. | Himanshu Kaul, Jae-sun Seo, Mark A. Anders, Dennis Sylvester, Ram Krishnamurthy |
| 2007 | ISLPED | A robust edge encoding technique for energy-efficient multi-cycle interconnect. | Jae-sun Seo, Dennis Sylvester, David T. Blaauw, Himanshu Kaul, Ram Krishnamurthy |