Jean-Michel Portal
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
39
Venues
9
Active years
1998–2023
Best venue rank
A
Where they publish
Papers
39 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2023 | ASPDAC | A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects. | Kamel-Eddine Harabi, Clement Trck, Marie Drouhin, Adrien Renaudineau, Thomas Bersani-Veroni, Damien Querlioz, Tifenn Hirtzlin, Elisa Vianello, Marc Bocquet, Jean-Michel Portal |
| 2023 | DATE | Binary ReRAM-based BNN first-layer implementation. | Mona Ezzadeen, Atreya Majumdar, Sigrid Thomas, Jean-Philippe Nol, Bastien Giraud, Marc Bocquet, Franois Andrieu, Damien Querlioz, Jean-Michel Portal |
| 2023 | DATE | Energy-Efficient Bayesian Inference Using Near-Memory Computation with Memristors. | Clement Trck, Kamel-Eddine Harabi, Tifenn Hirtzlin, Elisa Vianello, Raphal Laurent, Jacques Droulez, Pierre Bessire, Marc Bocquet, Jean-Michel Portal, Damien Querlioz |
| 2021 | DATE | Storage Class Memory with Computing Row Buffer: A Design Space Exploration. | Valentin Egloff, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, Csar Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean-Michel Portal |
| 2020 | DATE | Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing. | Jean-Philippe Nol, Valentin Egloff, Maha Kooli, Roman Gauchi, Jean-Michel Portal, Henri-Pierre Charles, Pascal Vivet, Bastien Giraud |
| 2020 | DATE | In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications. | Bogdan Penkovsky, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz |
| 2019 | IOLTS | Dual Detection of Heating and Photocurrent attacks (DDHP) Sensor using Hybrid CMOS/STT-MRAM. | Mounia Kharbouche-Harrari, Romain Wacquez, Gregory di Pendina, Jean-Max Dutertre, Jrmy Postel-Pellerin, Driss Aboulkassimi, Jean-Michel Portal |
| 2019 | ISCAS | Light-Weight Cipher Based on Hybrid CMOS/STT-MRAM: Power/Area Analysis. | Mounia Kharbouche-Harrari, Gregory di Pendina, Romain Wacquez, Bernard Dieny, Driss Aboulkassimi, Jrmy Postel-Pellerin, Jean-Michel Portal |
| 2018 | IOLTS | Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues. | Mounia Kharbouche-Harrari, Jrmy Postel-Pellerin, Gregory di Pendina, Romain Wacquez, Driss Aboulkassimi, Marc Bocquet, R. Sousa, R. Delattre, Jean-Michel Portal |
| 2018 | IOLTS | Resistive and Spintronic RAMs: Device, Simulation, and Applications. | Elena-Ioana Vatajelu, Lorena Anghel, Jean-Michel Portal, Marc Bocquet, Guillaume Prenat |
| 2017 | IOLTS | Thermal laser attack and high temperature heating on HfO2-based OxRAM cells. | Alexis Krakovinsky, Marc Bocquet, Romain Wacquez, Jean Coignus, Jean-Michel Portal |
| 2017 | ISCAS | Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. | Mahesh Nataraj, Alexandre Levisse, Bastien Giraud, Jean-Philippe Nol, Pascal Andreas Meinerzhagen, Jean-Michel Portal, Pierre-Emmanuel Gaillardon |
| 2014 | DATE | Resistive memories: Which applications? | Fabien Clermidy, Natalija Jovanovic, Santhosh Onkaraiah, Houcine Oucheikh, Olivier Thomas, Ogun Turkyilmaz, Elisa Vianello, Jean-Michel Portal, Marc Bocquet |
| 2014 | IOLTS | An innovative standard cells remapping method for in-circuit critical parameters monitoring. | Loic Welter, Philippe Dreux, Hassen Aziza, Jean-Michel Portal |
| 2013 | IOLTS | Embedded high-precision frequency-based capacitor measurement system. | Loic Welter, Philippe Dreux, Jean-Michel Portal, Hassen Aziza |
| 2013 | ISCAS | A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array. | Santhosh Onkaraiah, Ogun Turkyilmaz, Marina Reyboz, Fabien Clermidy, Elisa Vianello, Jean-Michel Portal, Christophe Muller |
| 2013 | VTS | On the investigation of built-in tuning of RF receivers using on-chip polyphase filters. | Fayrouz Haddad, Wenceslas Rahajandraibe, Hassen Aziza, Karine Castellani-Couli, Jean-Michel Portal |
| 2011 | ISCAS | Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area. | Y. Joly, L. Truphemus, Laurent Lopez, Jean-Michel Portal, Hassen Aziza, Franck Julien, Pascal Fornara |
| 2009 | DDECS | An on-line testing scheme for repairing purposes in Flash memories. | Olivier Ginez, Jean-Michel Portal, Hassen Aziza |
| 2009 | ETS | Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections. | Olivier Ginez, Jean-Michel Portal, Christophe Muller |
| 2008 | ITC | A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories. | Olivier Ginez, Jean-Michel Portal, Hassen Aziza |
| 2006 | ISCAS | MM11 based flash memory cell model including characterization procedure. | B. Saillet, Arnaud Rgnier, Jean-Michel Portal, B. Delsuc, Romain Laffont, Pascal Masson, Rachid Bouchakour |
| 2005 | DATE | A New Embedded Measurement Structure for eDRAM Capacitor. | Laurent Lopez, Jean-Michel Portal, Didier Ne |
| 2004 | DATE | A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology. | Sandrine Bernardini, Jean-Michel Portal, Pascal Masson |
| 2004 | ISCAS | Efficient hardware implementation of a CRYPTO-MEMORY based on AES algorithm and SRAM architecture. | Anna Labb, Annie Prez, Jean-Michel Portal |
| 2003 | ITC | Infrastructure IP for Back-End Yield Improvement. | L. Forli, Jean-Michel Portal, Didier Ne, Bertrand Borot |
| 2003 | ITC | EEPROM Memory: Threshold Voltage Built In Self Diagnosis. | Jean-Michel Portal, Hassen Aziza, Didier Ne |
| 2002 | ISCAS | Floating-gate EEPROM cell: threshold voltage sensibility to geometry. | Jean-Michel Portal, L. Forli, Didier Ne |
| 2002 | ISCAS | Floating-gate EEPROM cell model based on MOS model 9. | Jean-Michel Portal, L. Forli, Didier Ne |
| 2002 | ITC | An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell. | Jean-Michel Portal, L. Forli, Hassen Aziza, Didier Ne |
| 2001 | ETS | Analyzing bridging faults impact on EEPROM cell array. | Jean-Michel Portal, Annie Prez |
| 2001 | ITC | IS-FPGA : a new symmetric FPGA architecture with implicit scan. | Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 2000 | ETS | Analyzing the test generation problem for an application-oriented test of FPGAs. | Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian |
| 1999 | DATE | Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 1999 | ETS | Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 1998 | DATE | Novel Technique for Testing FPGAs. | Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi |
| 1998 | DATE | RAM-Based FPGA's: A Test Approach for the Configurable Logic. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 1998 | FPL | SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 1998 | ITC | SRAM-based FPGA's: testing the LUT/RAM modules. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |