| 2026 | ASPDAC | Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language. | Runzhi Wang, Prianka Sengupta, Cristhian Roman-Vicharra, Yiran Chen, Jiang Hu |
| 2026 | DATE | Machine Learning-Driven Early Performance Prediction Framework for Accelerated Microarchitecture Simulation. | Aiden Stickney, Osvaldo Castro, Aaron Chan, Paul V. Gratz, Jiang Hu, Aakash Tyagi, Jered Dominguez-Trujillo, Galen M. Shipman, Kevin Sheridan |
| 2026 | FCCM | LegoMap: Optimization for High-Throughput Transformer Computing on AI Engine-Based FPGAs. | Hailiang Hu, Haodong Chang, Donghao Fang, Zhenrui Wang, Wuxi Li, Rongjian Liang, Bo Yuan, Jiang Hu |
| 2025 | AAAI | Decentralized Projected Riemannian Stochastic Recursive Momentum Method for Nonconvex Optimization. | Kangkang Deng, Jiang Hu |
| 2025 | ASPDAC | PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot Detection. | Chen-Chia Chang, Wan-Hsuan Lin, Jingyu Pan, Guanglei Zhou, Zhiyao Xie, Jiang Hu, Yiran Chen |
| 2025 | DAC | PatternPaint: Practical Layout Pattern Generation Using Diffusion-Based Inpainting. | Guanglei Zhou, Bhargav Korrapati, Gaurav Rajavendra Reddy, Chen-Chia Chang, Jingyu Pan, Jiang Hu, Yiran Chen, Dipto G. Thakurta |
| 2025 | MICRO | Crane: Inter-Layer Scheduling Framework for DNN Inference and Training Co-Support on Tiled Architecture. | Yu Gong, Lingyi Huang, Haodong Chang, Rongjian Liang, Cheng Yang, Zhexiang Tang, Jiang Hu, Bo Yuan |
| 2024 | DATE | DiMO-Sparse: Differentiable Modeling and Optimization of Sparse CNN Dataflow and Hardware Architecture. | Jianfeng Song, Rongjian Liang, Yu Gong, Bo Yuan, Jiang Hu |
| 2024 | ICASSP | Composite Federated Learning with Heterogeneous Data. | Jiaojiao Zhang, Jiang Hu, Mikael Johansson |
| 2024 | ICCAD | SysMix: Mixed-Size Placement for Systolic-Array-Based Hierarchical Designs. | Donghao Fang, Hailiang Hu, Wuxi Li, Bo Yuan, Jiang Hu |
| 2024 | ISPASS | Aiding Microprocessor Performance Validation with Machine Learning. | Erick Carvajal Barboza, Mahesh Ketkar, Paul Gratz, Jiang Hu |
| 2024 | ISSTA | Identifying Smart Contract Security Issues in Code Snippets from Stack Overflow. | Jiachi Chen, Chong Chen, Jiang Hu, John C. Grundy, Yanlin Wang, Ting Chen, Zibin Zheng |
| 2023 | ASPDAC | Rethink before Releasing Your Model: ML Model Extraction Attack in EDA. | Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Jiang Hu, Yiran Chen |
| 2023 | ASPDAC | Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction. | Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Yaguang Li, Yishuang Lin, Jiang Hu, Yiran Chen |
| 2023 | ASPDAC | BufFormer: A Generative ML Framework for Scalable Buffering. | Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, Haoxing Ren |
| 2023 | DAC | Lightning Talk: Power and Performance Reconciliation - from Tradeoff to Win-Win. | Jiang Hu |
| 2023 | ICCAD | Systolic Array Placement on FPGAs. | Hailiang Hu, Donghao Fang, Wuxi Li, Bo Yuan, Jiang Hu |
| 2023 | ICCAD | Invited Paper: The Inevitability of AI Infusion Into Design Closure and Signoff. | Jiang Hu, Andrew B. Kahng |
| 2023 | ISLPED | Scaled Population Division for Approximate Computing. | Kunal Bharathi, Sunil P. Khatri, Jiang Hu |
| 2022 | ASPDAC | Mapping Large Scale Finite Element Computing on to Wafer-Scale Engines. | Yishuang Lin, Rongjian Liang, Yaguang Li, Hailiang Hu, Jiang Hu |
| 2022 | DAC | Towards collaborative intelligence: routability estimation based on decentralized private data. | Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen |
| 2022 | DATE | Are Analytical Techniques Worthwhile for Analog IC Placement? | Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu |
| 2022 | FPL | TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations. | Chan-Wei Hu, Jiang Hu, Sunil P. Khatri |
| 2022 | ICCAD | Deep Learning Toolkit-Accelerated Analytical Co-Optimization of CNN Hardware and Dataflow. | Rongjian Liang, Jianfeng Song, Bo Yuan, Jiang Hu |
| 2022 | ICCAD | A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions. | Rongjian Liang, Hua Xiang, Jinwook Jung, Jiang Hu, Gi-Joon Nam |
| 2022 | ICCAD | Robustify ML-Based Lithography Hotspot Detectors. | Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Jiang Hu, Yiran Chen |
| 2022 | ICCAD | How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning. | Prianka Sengupta, Aakash Tyagi, Yiran Chen, Jiang Hu |
| 2022 | ICCAD | DEEP: Developing Extremely Efficient Runtime On-Chip Power Meters. | Zhiyao Xie, Shiyu Li, Mingyuan Ma, Chen-Chia Chang, Jingyu Pan, Yiran Chen, Jiang Hu |
| 2021 | ASPDAC | Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. | Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar |
| 2021 | ASPDAC | Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation. | Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, Yiran Chen |
| 2021 | DATE | Analog Layout Generation using Optimized Primitives. | Meghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani |
| 2021 | HPCA | Automatic Microprocessor Performance Bug Detection. | Erick Carvajal Barboza, Sara Jacob, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz, Jiang Hu |
| 2021 | ICCAD | Automatic Routability Predictor Development Using Neural Architecture Search. | Chen-Chia Chang, Jingyu Pan, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chung-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen |
| 2021 | ICCAD | FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer. | Rongjian Liang, Jinwook Jung, Hua Xiang, Lakshmi N. Reddy, Alexey Lvov, Jiang Hu, Gi-Joon Nam |
| 2021 | ICCAD | From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. | Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen |
| 2021 | MICRO | APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors. | Zhiyao Xie, Xiaoqing Xu, Matt Walker, Joshua Knebel, Kumaraguru Palaniswamy, Nicolas Hebert, Jiang Hu, Huanrui Yang, Yiran Chen, Shidhartha Das |
| 2020 | ASPDAC | FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. | Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza |
| 2020 | ASPDAC | PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. | Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen |
| 2020 | ASPDAC | Enhancing Generalization of Wafer Defect Detection by Data Discrepancy-aware Preprocessing and Contrast-varied Augmentation. | Chaofei Yang, Hai Li, Yiran Chen, Jiang Hu |
| 2020 | ASPDAC | Scaled Population Arithmetic for Efficient Stochastic Computing. | He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu |
| 2020 | DATE | GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. | Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar |
| 2020 | ICCAD | The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). | Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar |
| 2020 | ICCAD | Routing-Free Crosstalk Prediction. | Rongjian Liang, Zhiyao Xie, Jinwook Jung, Vishnavi Chauha, Yiran Chen, Jiang Hu, Hua Xiang, Gi-Joon Nam |
| 2020 | ICCAD | A Customized Graph Neural Network Model for Guiding Analog IC Placement. | Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu |
| 2020 | ICCAD | Fast IR Drop Estimation with Machine Learning : Invited Paper. | Zhiyao Xie, Hai Li, Xiaoqing Xu, Jiang Hu, Yiran Chen |
| 2020 | ICCCI | Predicting National Basketball Association Players Performance and Popularity: A Data Mining Approach. | Nguyen Nguyen, Bingkun Ma, Jiang Hu |
| 2020 | ICCD | Scaled Population Subtraction for Approximate Computing. | Kunal Bharathi, Jiang Hu, Sunil P. Khatri |
| 2020 | ITC | Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits. | Adriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, Sir Yee Lee, Edgar Snchez-Sinencio, Jiang Hu, Jeyavijayan (JV) Rajendran |
| 2019 | ASPDAC | SeFAct: selective feature activation and early classification for CNNs. | Farhana Sharmin Snigdha, Ibrahim Ahmed, Susmita Dey Manasi, Meghna G. Mankalale, Jiang Hu, Sachin S. Sapatnekar |
| 2019 | ASPDAC | Layout recognition attacks on split manufacturing. | Wenbin Xu, Lang Feng, Jeyavijayan Rajendran, Jiang Hu |
| 2019 | DAC | Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism. | Erick Carvajal Barboza, Nishchal Shukla, Yiran Chen, Jiang Hu |
| 2019 | DAC | ALIGN: Open-Source Analog Layout Automation from the Ground Up. | Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar |
| 2019 | DAC | A Memory-Efficient Markov Decision Process Computation Framework Using BDD-based Sampling Representation. | He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu |
| 2019 | DATE | Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model. | Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu |
| 2019 | ITC | Breaking Analog Locking Techniques via Satisfiability Modulo Theories. | Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Snchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran |
| 2019 | RTCSA | Improving QoS for Global Dual-Criticality Scheduling on Multiprocessors. | Lin Huang, I-Hong Hou, Sachin S. Sapatnekar, Jiang Hu |
| 2019 | RV | FastCFI: Real-Time Control Flow Integrity Using FPGA Without Code Instrumentation. | Lang Feng, Jeff Huang, Jiang Hu, Abhijith Reddy |
| 2018 | DAC | Using imprecise computing for improved non-preemptive real-time scheduling. | Lin Huang, Youmeng Li, Sachin S. Sapatnekar, Jiang Hu |
| 2018 | ICCAD | Towards provably-secure analog and mixed-signal locking against overproduction. | Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Snchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran |
| 2018 | ICCAD | RouteNet: routability prediction for mixed-size designs using convolutional neural network. | Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu |
| 2018 | RTNS | Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems. | Lin Huang, I-Hong Hou, Sachin S. Sapatnekar, Jiang Hu |
| 2017 | ASPDAC | Routing perturbation for enhanced security in split manufacturing. | Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan (JV) Rajendran |
| 2017 | CASES | A quantifiable approach to approximate computing: special session. | Chaofan Li, Deepashree Sengupta, Farhana Sharmin Snigdha, Wenbin Xu, Jiang Hu, Sachin S. Sapatnekar |
| 2017 | DAC | SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits. | Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar |
| 2017 | ICCAD | Making split fabrication synergistically secure and manufacturable. | Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran |
| 2017 | ICCAD | Making split fabrication synergistically secure and manufacturable. | Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran |
| 2017 | ICCAD | Front-end-of-line attacks in split manufacturing. | Yujie Wang, Tri Cao, Jiang Hu, Jeyavijayan Rajendran |
| 2017 | ISLPED | A simple yet efficient accuracy configurable adder design. | Wenbin Xu, Sachin S. Sapatnekar, Jiang Hu |
| 2017 | ISPA | Reinforcement Learning Control for Water-Efficient Agricultural Irrigation. | Lijia Sun, Yanxiang Yang, Jiang Hu, Dana Porter, Thomas H. Marek, Charles Hillyer |
| 2017 | ISPA | A Reliable Soil Moisture Sensing Methodology for Agricultural Irrigation. | Yanxiang Yang, Lijia Sun, Jiang Hu, Dana Porter, Thomas H. Marek, Charles Hillyer |
| 2017 | ITC | Thwarting analog IC piracy via combinational locking. | Jiafan Wang, Congyin Shi, Adriana C. Sanabria-Borbon, Edgar Snchez-Sinencio, Jiang Hu |
| 2017 | UIC | A comparative study on neural network-based prediction of smart community energy consumption. | Lijia Sun, Jiang Hu, Yang Liu, Lin Liu, Shiyan Hu |
| 2016 | DAC | Optimal design of JPEG hardware under the approximate computing paradigm. | Farhana Sharmin Snigdha, Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar |
| 2016 | DAC | The cat and mouse in split manufacturing. | Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan Rajendran |
| 2016 | ICCAD | Control synthesis and delay sensor deployment for efficient ASV designs. | Chaofan Li, Sachin S. Sapatnekar, Jiang Hu |
| 2015 | DAC | Joint precision optimization and high level synthesis for approximate computing. | Chaofan Li, Wei Luo, Sachin S. Sapatnekar, Jiang Hu |
| 2015 | DATE | Timing verification for adaptive integrated circuits. | Rohit Kumar, Bing Li, Yiren Shen, Ulf Schlichtmann, Jiang Hu |
| 2015 | ICCD | GPU acceleration for PCA-based statistical static timing analysis. | Yiren Shen, Jiang Hu |
| 2015 | ICCD | A pre-search assisted ILP approach to analog integrated circuit routing. | Chia-Yu Wu, Helmut Graeb, Jiang Hu |
| 2015 | ISLPED | Collaborative gate implementation selection and adaptivity assignment for robust combinational circuits. | Hao He, Jiafan Wang, Jiang Hu |
| 2015 | ISLPED | Having your cake and eating it too: Energy savings without performance loss through resource sharing driven power management. | Jae-Yeon Won, Paul Gratz, Srinivas Shakkottai, Jiang Hu |
| 2014 | HPCA | Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management. | Jae-Yeon Won, Xi Chen, Paul Gratz, Jiang Hu, Vassos Soteriou |
| 2014 | ISLPED | Algorithms for power-efficient QoS in application specific NoCs. | Hao He, Gongming Yang, Jiang Hu |
| 2013 | DAC | Dynamic voltage and frequency scaling for shared resources in multicore processor designs. | Xi Chen, Zheng Xu, Hyungjun Kim, Paul V. Gratz, Jiang Hu, Michael Kishinevsky, mit Y. Ogras, Raid Zuhair Ayoub |
| 2013 | ICCD | Power gating with block migration in chip-multiprocessor last-level caches. | David Kadjo, Hyungjun Kim, Paul Gratz, Jiang Hu, Raid Ayoub |
| 2013 | ICCD | Resource allocation algorithms for guaranteed service in application-specific NoCs. | Gongming Yang, Hao He, Jiang Hu |
| 2012 | ICCD | Track assignment considering crosstalk-induced performance degradation. | Qiong Zhao, Jiang Hu |
| 2011 | ICCAD | Gate sizing and device technology selection algorithms for high-performance industrial designs. | Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu |
| 2010 | ASPDAC | Physical design techniques for optimizing RTA-induced variations. | Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar |
| 2010 | DAC | Detecting tangled logic structures in VLSI netlists. | Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn |
| 2010 | DATE | SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal. | Fan Yang, Yici Cai, Qiang Zhou, Jiang Hu |
| 2010 | ICCAD | Clustering-based simultaneous task and voltage scheduling for NoC systems. | Yifang Liu, Yu Yang, Jiang Hu |
| 2009 | DAC | GPU-based parallelization for fast circuit optimization. | Yifang Liu, Jiang Hu |
| 2008 | ASPDAC | Handling partial correlations in yield prediction. | Sridhar Varadan, Janet Meiling Wang, Jiang Hu |
| 2008 | ASPDAC | Low power clock buffer planning methodology in F-D placement for large scale circuit design. | Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian |
| 2008 | ICCAD | Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. | Yifang Liu, Rupesh S. Shelar, Jiang Hu |
| 2008 | ICCD | Gate planning during placement for gated clock network. | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
| 2007 | ASPDAC | A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. | Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman |
| 2007 | CHI | Context & usability testing: user-modeled information presentation in easy and difficult driving conditions. | Jiang Hu, Andi Winterboer, Clifford Nass, Johanna D. Moore, Rebecca Illowsky |
| 2007 | DAC | Gate Sizing For Cell Library-Based Designs. | Shiyan Hu, Mahesh Ketkar, Jiang Hu |
| 2007 | ICCAD | Unified adaptivity optimization of clock and logic signals. | Shiyan Hu, Jiang Hu |
| 2007 | ICCAD | Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. | Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu |
| 2007 | ICCAD | Modeling, optimization and control of rotary traveling-wave oscillator. | Cheng Zhuo, Huafeng Zhang, Rupak Samanta, Jiang Hu, Kangsheng Chen |
| 2007 | Interspeech | The influence of user tailoring and cognitive load on user performance in spoken dialogue systems. | Andi Winterboer, Jiang Hu, Johanna D. Moore, Clifford Nass |
| 2007 | VLSID | A Placement Methodology for Robust Clocking. | Ganesh Venkataraman, Jiang Hu |
| 2006 | CHI | groupTime: preference based group scheduling. | Mike Brzozowski, Kendra Carattini, Scott R. Klemmer, Patrick Mihelich, Jiang Hu, Andrew Y. Ng |
| 2006 | CHI | Adaptive language behavior in HCI: how expectations and beliefs about a system affect users' word choice. | Jamie Pearson, Jiang Hu, Holly P. Branigan, Martin J. Pickering, Clifford Nass |
| 2006 | DAC | Standard cell characterization considering lithography induced variations. | Ke Cao, Sorin Dobre, Jiang Hu |
| 2006 | DAC | Fast algorithms for slew constrained minimum cost buffering. | Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze |
| 2006 | DAC | Steiner network construction for timing critical nets. | Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li |
| 2006 | DATE | Associative skew clock routing for difficult instances. | Min-Seok Kim, Jiang Hu |
| 2006 | DATE | Integrated placement and skew optimization for rotary clocking. | Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze |
| 2006 | ICCAD | A new RLC buffer insertion algorithm. | Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi |
| 2006 | ICCAD | Clock buffer polarity assignment for power noise reduction. | Rupak Samanta, Ganesh Venkataraman, Jiang Hu |
| 2006 | ICCAD | Combinatorial algorithms for fast clock mesh optimization. | Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li |
| 2006 | ICCAD | Fast decap allocation based on algebraic multigrid. | Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen |
| 2006 | ISCAS | High performance clock routing in X-architecture. | Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu |
| 2005 | ASPDAC | Library cell layout with Alt-PSM compliance and composability. | Ke Cao, Puneet Dhawan, Jiang Hu |
| 2005 | ASPDAC | Clock network minimization methodology based on incremental placement. | Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu |
| 2005 | ASPDAC | Making fast buffer insertion even faster via approximation techniques. | Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi |
| 2005 | ASPDAC | Register placement for low power clock network. | Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu |
| 2005 | ASPDAC | Skew scheduling and clock routing for improved tolerance to process variations. | Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu |
| 2005 | ASPDAC | Timing driven track routing considering coupling capacitance. | Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra |
| 2005 | DAC | Navigating registers in placement for clock network minimization. | Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu |
| 2005 | DAC | Path based buffer insertion. | Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi |
| 2005 | ICCAD | Practical techniques to reduce skew and its variations in buffered clock networks. | Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert |
| 2005 | ICCAD | DiCER: distributed and cost-effective redundancy for variation tolerance. | Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, Rabi N. Mahapatra |
| 2005 | Interact | Preference-Based Group Scheduling. | Jiang Hu, Mike Brzozowski |
| 2005 | Interact | Natural Language Query vs. Keyword Search: Effects of Task Complexity on Search Performance, Participant Perceptions, and Preferences. | QianYing Wang, Clifford Nass, Jiang Hu |
| 2004 | ASPDAC | A place and route aware buffered Steiner tree construction. | Cliff C. N. Sze, Jiang Hu, Charles J. Alpert |
| 2004 | ASPDAC | Layer assignment for crosstalk risk minimization. | Di Wu, Jiang Hu, Rabi N. Mahapatra, Min Zhao |
| 2004 | DAC | Fast and flexible buffer trees that navigate the physical layout environment. | Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay |
| 2004 | DAC | Reducing clock skew variability via cross links. | Anand Rajaram, Jiang Hu, Rabi N. Mahapatra |
| 2004 | ICCAD | Accurate estimation of global buffer delay within a floorplan. | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze |
| 2004 | ICCAD | Exploiting level sensitive latches in wire pipelining. | V. Seth, Min Zhao, Jiang Hu |
| 2003 | ICCAD | Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. | Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu |
| 2003 | ICCD | A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing. | Rishi Chaturvedi, Jiang Hu |
| 2002 | DAC | Congestion-driven codesign of power and signal networks. | Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif |
| 2001 | DAC | A Practical Methodology for Early Buffer and Wire Resource Allocation. | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia |
| 2001 | ICCD | Performance Driven Global Routing Through Gradual Refinement. | Jiang Hu, Sachin S. Sapatnekar |
| 2001 | ISCAS | Steiner tree optimization for buffers. Blockages and bays. | Charles J. Alpert, Gopal Gandham, Jiang Hu, Jos Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar |
| 2000 | ICCAD | A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. | Jiang Hu, Sachin S. Sapatnekar |
| 1999 | DAC | FAR-DS: Full-Plane AWE Routing with Driver Sizing. | Jiang Hu, Sachin S. Sapatnekar |