| 2021 | ASPDAC | 1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method. | Li-Cheng Zheng, Hao-Ju Chang, Yung-Chih Chen, Jing-Yang Jou |
| 2021 | DATE | Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design. | Hao-Yu Chi, Han-Chung Chang, Chih-Hsin Yang, Chien-Nan Liu, Jing-Yang Jou |
| 2016 | ASPDAC | Chain-based pin count minimization for general-purpose digital microfluidic biochips. | Yung-Chun Lei, Chen-Shing Hsu, Juinn-Dar Huang, Jing-Yang Jou |
| 2016 | DATE | Resource-aware functional ECO patch generation. | An-Che Cheng, Iris Hui-Ru Jiang, Jing-Yang Jou |
| 2016 | ISCAS | Wave digital filter based analog circuit emulation on FPGA. | Wei Wu, Yen-Lung Chen, Yue Ma, Chien-Nan Jimmy Liu, Jing-Yang Jou, Sudhakar Pamarti, Lei He |
| 2014 | ASPDAC | A read-write aware DRAM scheduling for power reduction in multi-core systems. | Chih-Yen Lai, Gung-Yu Pan, Hsien-Kai Kuo, Jing-Yang Jou |
| 2014 | ICCAD | A learning-on-cloud power management policy for smart devices. | Gung-Yu Pan, Bo-Cheng Charles Lai, Sheng-Yen Chen, Jing-Yang Jou |
| 2013 | ASPDAC | Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs. | Hsien-Kai Kuo, Ta-Kan Yen, Bo-Cheng Charles Lai, Jing-Yang Jou |
| 2012 | ASPDAC | Thread affinity mapping for irregular data access on shared Cache GPGPU. | Hsien-Kai Kuo, Kuan-Ting Chen, Bo-Cheng Charles Lai, Jing-Yang Jou |
| 2011 | ASPDAC | Equivalence checking of scheduling with speculative code transformations in high-level synthesis. | Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou |
| 2011 | ITC | Design-for-debug layout adjustment for FIB probing and circuit editing. | Kuo-An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango Chia-Tso Chao, Jing-Yang Jou, Sonair Chen |
| 2009 | VTS | Multiple-Fault Diagnosis Using Faulty-Region Identification. | Meng-Jai Tasi, Mango Chia-Tso Chao, Jing-Yang Jou, Meng-Chen Wu |
| 2007 | ASPDAC | A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. | Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou |
| 2006 | ASPDAC | A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. | Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou |
| 2006 | ASPDAC | FSM-based transaction-level functional coverage for interface compliance verification. | Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou |
| 2005 | ASPDAC | An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. | Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou |
| 2005 | ASPDAC | Communication-driven task binding for multiprocessor with latency insensitive network-on-chip. | Liang-Yu Lin, Cheng-Yeh Wang, Pao-Jui Huang, Chih-Chieh Chou, Jing-Yang Jou |
| 2005 | ISCAS | Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. | Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou |
| 2005 | ISCAS | RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang |
| 2004 | ASPDAC | Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming. | Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou |
| 2004 | ASPDAC | On compliance test of on-chip bus for SOC. | Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou |
| 2004 | ASPDAC | Layout techniques for on-chip interconnect inductance reduction. | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang |
| 2004 | ICCD | Graph Automorphism-Based Algorithm for Determining Symmetric Inputs. | Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou |
| 2004 | ISCAS | An efficient logic extraction algorithm using partitioning and circuit encoding. | Lily Huang, Tai-Ying Jiang, Jing-Yang Jou, Heng-Liang Huang |
| 2004 | ISCAS | An efficient approach for hierarchical submodule extraction. | Yi-Wei Lin, Jing-Yang Jou |
| 2004 | ISCAS | RLC effects on worst-case switching pattern for on-chip buses. | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang |
| 2004 | ITC | Verification on Port Connections. | Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang |
| 2003 | ASPDAC | An efficient IP-level power model for complex digital circuits. | Chih-Yang Hsu, Chien-Nan Jimmy Liu, Jing-Yang Jou |
| 2003 | ASPDAC | Simultaneous floorplanning and buffer block planning. | Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao |
| 2003 | ASPDAC | An automatic interconnection rectification technique for SoC design integration. | Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou |
| 2003 | ISCAS | An efficient approach for error diagnosis in HDL design. | Che-Hua Shih, Jing-Yang Jou |
| 2003 | ISCAS | SoC design integration by using automatic interconnection rectification. | Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou |
| 2001 | ASPDAC | An efficient design-for-verification technique for HDLs. | Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou |
| 2001 | ISCAS | Grouped input power sensitive transition an input sequence compaction technique for power estimation. | Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen |
| 2001 | ISCAS | On tri-state buffer inference in HDL synthesis. | Hen-Ming Lin, Jing-Yang Jou |
| 2001 | ISCAS | An AVPG for SOC design verification with port order fault model. | Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou |
| 2000 | ASPDAC | A new method for constructing IP level power model based on power sensitivity. | Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou |
| 2000 | ISCAS | A novel approach for functional coverage measurement in HDL. | Chien-Nan Jimmy Liu, Chen-Yi Chang, Jing-Yang Jou, Ming-Chih Lai, Hsing-Ming Juan |
| 1999 | ASPDAC | Hierarchical Floorplan Design on the Internet. | Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang |
| 1999 | DAC | Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. | Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang |
| 1999 | ICCD | Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD. | Hen-Ming Lin, Jing-Yang Jou |
| 1999 | ICCD | An Efficient Functional Coverage Test for HDL Descriptions at RTL. | Chien-Nan Jimmy Liu, Jing-Yang Jou |
| 1998 | DAC | Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. | Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang |
| 1997 | ASPDAC | BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. | Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei |
| 1997 | ASPDAC | A power driven two-level logic optimizer. | Jyh-Mou Tseng, Jing-Yang Jou |
| 1997 | ICCAD | A power modeling and characterization method for macrocells using structure information. | Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou |
| 1997 | ICCD | Power Driven Partial Scan. | Jing-Yang Jou, Ming-Chang Nien |
| 1996 | ICCAD | An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. | Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen |
| 1996 | ICCAD | A power modeling and characterization method for the CMOS standard cell library. | Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou |
| 1995 | ICCAD | Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. | Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen |
| 1991 | ICCAD | Timing-Driven Partial Scan. | Jing-Yang Jou, Kwang-Ting Cheng |
| 1990 | ICCAD | A Single-State-Transition Fault Model for Sequential Machines. | Kwang-Ting Cheng, Jing-Yang Jou |
| 1990 | ITC | Functional test generation for finite state machines. | Kwang-Ting Cheng, Jing-Yang Jou |
| 1989 | ICCD | OPAM: an efficient output phase assignment for multilevel logic minimization. | Chin-Long Wey, Sin-Min Chang, Jing-Yang Jou |
| 1988 | DAC | BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping. | Ruey-Sing Wei, Steven G. Rothweiler, Jing-Yang Jou |
| 1988 | ICCD | A testable PLA design with low overhead and ease of test generation. | Jing-Yang Jou |
| 1988 | ICPP | Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing. | Jing-Yang Jou, Jacob A. Abraham |