| 2026 | VLSID | An Instruction-Set-Based Processor Design for Scalable Post-Quantum Cryptography: A Case Study with Baby Kyber. | Ramyavani P, Radhanath Mishra, Abhiram Karanam, Amit Kumar Panda, G. Geethakumari, Joseph Zambreno, Subhendu Kumar Sahoo |
| 2019 | FCCM | Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms. | Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones, Kristof Denolf, Jack Lo, Kees A. Vissers |
| 2018 | FPL | A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature Descriptors. | Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones |
| 2018 | ICPP | Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection. | Xian Zhu, Robert Wernsman, Joseph Zambreno |
| 2018 | RTSS | Work-in-Progress: Real-Time Modeling for Intrusion Detection in Automotive Controller Area Network. | Habeeb Olufowobi, Gedare Bloom, Clinton Young, Joseph Zambreno |
| 2016 | FIE | Evidence-based planning to broaden the participation of women in electrical and computer engineering. | Diane T. Rover, Joseph Zambreno, Mani Mina, Phillip H. Jones, Lora Leigh Chrystal |
| 2016 | ICCD | Parallelizing Latent Semantic Indexing using an FPGA-based architecture. | Xinying Wang, Joseph Zambreno |
| 2016 | ICCD | ONAC: Optimal number of active cores detector for energy efficient GPU computing. | Xian Zhu, Mihir Awatramani, Diane T. Rover, Joseph Zambreno |
| 2015 | FPL | A software configurable coprocessor-based state-space controller. | Aaron Mills, Pei Zhang, Sudhanshu Vyas, Joseph Zambreno, Phillip H. Jones |
| 2014 | FCCM | An Efficient Architecture for Floating-Point Eigenvalue Decomposition. | Xinying Wang, Joseph Zambreno |
| 2014 | ICCD | Cache design for mixed criticality real-time systems. | N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones |
| 2014 | MEMOCODE | A high performance systolic architecture for k-NN classification. | Kevin Townsend, Phillip H. Jones, Joseph Zambreno |
| 2013 | COMAD | Polarity Trend Analysis of Public Sentiment on YouTube. | Amar Krishna, Joseph Zambreno, Sandeep Krishnan |
| 2013 | ICCD | Increasing GPU throughput using kernel interleaved thread block scheduling. | Mihir Awatramani, Joseph Zambreno, Diane T. Rover |
| 2013 | ICCS | Scheduling Challenges in Mixed Critical Real-Time Heterogeneous Computing Platforms. | Chetan Kumar N. G., Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones |
| 2013 | VTS | A multi-faceted approach to FPGA-based Trojan circuit detection. | Michael Patterson, Aaron Mills, Ryan A. Scheel, Julie Tillman, Evan Dye, Joseph Zambreno |
| 2012 | ICCD | Design and evaluation of a delay-based FPGA Physically Unclonable Function. | Aaron Mills, Sudhanshu Vyas, Michael Patterson, Christopher Sabotta, Phillip H. Jones, Joseph Zambreno |
| 2012 | MEMOCODE | Shepard: A fast exact match short read aligner. | Chad Nelson, Kevin Townsend, Bhavani Satyanarayana Rao, Phillip H. Jones, Joseph Zambreno |
| 2011 | ICCD | Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection. | Justin Rilling, David Graziano, Jamin Hitchcock, Tim Meyer, Xinying Wang, Phillip H. Jones, Joseph Zambreno |
| 2011 | ISM | Using Chaotic Maps for Encrypting Image and Video Content. | Amit Pande, Prasant Mohapatra, Joseph Zambreno |
| 2010 | DATE | Detecting/preventing information leakage on the memory bus due to malicious hardware. | Abhishek Das, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary |
| 2010 | MEMOCODE | CANSCID-CUDA. | Michael Steffen, Veerendra Allada, Phillip H. Jones, Joseph Zambreno |
| 2010 | MICRO | Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels. | Michael Steffen, Joseph Zambreno |
| 2010 | VLSID | A Reconfigurable Architecture for Secure Multimedia Delivery. | Amit Pande, Joseph Zambreno |
| 2009 | CCS | Hardware-enforced fine-grained isolation of untrusted code. | Eugen Leontie, Gedare Bloom, Bhagirath Narahari, Rahul Simha, Joseph Zambreno |
| 2008 | DATE | An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System. | Abhishek Das, Sanchit Misra, Sumeet Joshi, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary |
| 2008 | FPL | Polymorphic wavelet architectures using reconfigurable hardware. | Amit Pande, Joseph Zambreno |
| 2008 | FPL | Mining Association Rules with systolic trees. | Song Sun, Joseph Zambreno |
| 2008 | MICRO | Evaluating the effects of cache redundancy on profit. | Abhishek Das, Berkin zisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary |
| 2007 | DATE | Interactive presentation: An FPGA implementation of decision tree classification. | Ramanathan Narayanan, Daniel Honbo, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno |
| 2007 | ICCS | Quantization Error and Accuracy-Performance Tradeoffs for Embedded Data Mining Workloads. | Ramanathan Narayanan, Berkin zisikyilmaz, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno |
| 2005 | FCCM | Exploiting Multi-Grained Parallelism in Reconfigurable SBC Architectures. | Joseph Zambreno, Daniel Honbo, Alok N. Choudhary |
| 2005 | ISI | CODESSEAL: Compiler/FPGA Approach to Secure Applications. | Olga Gelbart, Paul Ott, Bhagirath Narahari, Rahul Simha, Alok N. Choudhary, Joseph Zambreno |
| 2005 | ISI | Performance Study of a Compiler/Hardware Approach to Embedded Systems Security. | Kripashankar Mohan, Bhagirath Narahari, Rahul Simha, Paul Ott, Alok N. Choudhary, Joseph Zambreno |
| 2004 | DATE | Flexible Software Protection Using Hardware/Software Codesign Techniques. | Joseph Zambreno, Alok N. Choudhary, Rahul Simha, Bhagirath Narahari |
| 2004 | FPGA | Addressing application integrity attacks using a reconfigurable architecture. | Joseph Zambreno, Rahul Simha, Alok N. Choudhary |
| 2004 | FPL | Flow Monitoring in High-Speed Networks with 2D Hash Tables. | David Nguyen, Joseph Zambreno, Gokhan Memik |
| 2004 | FPL | Design and Evaluation of an FPGA Architecture for Software Protection. | Joseph Zambreno |
| 2004 | FPL | Exploring Area/Delay Tradeoffs in an AES FPGA Implementation. | Joseph Zambreno, David Nguyen, Alok N. Choudhary |
| 2002 | CASES | Optimizing inter-nest data locality. | Mahmut T. Kandemir, Ismail Kadayif, Alok N. Choudhary, Joseph Zambreno |
| 2002 | EMSOFT | Enhancing Compiler Techniques for Memory Energy Optimizations. | Joseph Zambreno, Mahmut T. Kandemir, Alok N. Choudhary |