Skip to content

Lars Bauer

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

55

Venues

13

Active years

2007–2026

Best venue rank

A*

Where they publish

Papers

55 indexed papers, newest first.

YearVenueTitleAuthors
2026DATEMIQARA: Mixed-Criticality Queue-based Architecture for Reconfigurable Accelerator Platforms.Hassan Nassar, Martin Rapp, Lars Bauer, Mostafa Elshimy, Zeynep Demirdag, Jrg Henkel
2025ASPDACThrough Fabric: A Cross-world Thermal Covert Channel on TEE-enhanced FPGA-MPSoC Systems.Hassan Nassar, Jeferson Gonzlez-Gmez, Varun Manjunath, Lars Bauer, Jrg Henkel
2025DATEHardware/Software Co-Analysis for Worst Case Execution Time Bounds.Can Joshua Lehmann, Lars Bauer, Hassan Nassar, Heba Khdr, Jrg Henkel
2024FCCMHBMorphic: FHE Acceleration via HBM-Enabled Recursive Karatsuba Multiplier on FPGA.Hassan Nassar, Lars Bauer, Jrg Henkel
2024FPGACovert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert Channels.Hassan Nassar, Philipp Machauer, Dennis R. E. Gnad, Lars Bauer, Mehdi B. Tahoori, Jrg Henkel
2024ICCADCo-Designing NVM-based Systems for Machine Learning and In-memory Search Applications.Jrg Henkel, Lokesh Siddhu, Hassan Nassar, Lars Bauer, Jian-Jia Chen, Christian Hakert, Tristan Taylan Seidl, Kuan-Hsun Chen, Xiaobo Sharon Hu, Mengyuan Li, Chia-Lin Yang, Ming-Liang Wei
2024ICCADDoS-FPGA: Denial of Service on Cloud FPGAs via Coordinated Power Hammering.Hassan Nassar, Philipp Machauer, Lars Bauer, Dennis Gnad, Mehdi Baradaran Tahoori, Jrg Henkel
2023CASESSpecial Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications.Jrg Henkel, Lokesh Siddhu, Lars Bauer, Jrgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jernimo Castrilln, Asif Ali Khan, Hamid Farzaneh, Joo Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng
2023DACSmart Detection of Obfuscated Thermal Covert Channel Attacks in Many-core Processors.Jeferson Gonzlez-Gmez, Mohammed Bakr Sikal, Heba Khdr, Lars Bauer, Jrg Henkel
2023DACLate Breaking Results: Configurable Ring Oscillators as a Side-Channel Countermeasure.Hassan Nassar, Simon Pankner, Lars Bauer, Jrg Henkel
2023DATEThe First Concept and Real-world Deployment of a GPU-based Thermal Covert Channel: Attack and Countermeasures.Jeferson Gonzlez-Gmez, Kevin Cordero-Zuiga, Lars Bauer, Jrg Henkel
2021DATETiVaPRoMi: Time-Varying Probabilistic Row-Hammer Mitigation.Hassan Nassar, Lars Bauer, Jrg Henkel
2021ICCADLoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs.Hassan Nassar, Hanna AlZughbi, Dennis R. E. Gnad, Lars Bauer, Mehdi B. Tahoori, Jrg Henkel
2019DATEDMRM: Distributed Market-Based Resource Management of Edge Computing Systems.Manolis Katsaragakis, Dimosthenis Masouros, Vasileios Tsoutsouras, Farzad Samie, Lars Bauer, Jrg Henkel, Dimitrios Soudris
2019EMSOFTAnalyses and architectures for mixed-critical systems: industry trends and research perspective.Lars Bauer, Marvin Damschen, Dirk Ziegenbein, Arne Hamann, Alessandro Biondi, Giorgio C. Buttazzo, Jrg Henkel
2019ICCADWCET Guarantees for Opportunistic Runtime Reconfiguration.Marvin Damschen, Lars Bauer, Jrg Henkel
2018DATEHighly efficient and accurate seizure prediction on constrained IoT devices.Farzad Samie, Sebastian Paul, Lars Bauer, Jrg Henkel
2017DATEUltra-low power and dependability for IoT devices (Invited paper for IoT technologies).Jrg Henkel, Santiago Pagani, Hussam Amrouch, Lars Bauer, Farzad Samie
2017EuroParShallow Water Waves on a Deep Technology Stack: Accelerating a Finite Volume Tsunami Model Using Reconfigurable Hardware in Invasive Computing.Alexander Pppl, Marvin Damschen, Florian Schmaus, Andreas Fried, Manuel Mohr, Matthias Blankertz, Lars Bauer, Jrg Henkel, Wolfgang Schrder-Preikschat, Michael Bader
2016DACResource budgeting for reliability in reconfigurable architectures.Hongyan Zhang, Lars Bauer, Jrg Henkel
2015DATEAdaptive on-the-fly application performance modeling for many cores.Sebastian Kobbe, Lars Bauer, Jrg Henkel
2015DATEOnline binding of applications to multiple clock domains in shared FPGA-based systems.Farzad Samie, Lars Bauer, Chih-Ming Hsieh, Jrg Henkel
2015ICCADSTRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures.Hongyan Zhang, Michael A. Kochte, Eric Schneider, Lars Bauer, Hans-Joachim Wunderlich, Jrg Henkel
2014CASESCOREFAB: Concurrent reconfigurable fabric utilization in heterogeneous multi-core systems.Artjom Grudnitsky, Lars Bauer, Jrg Henkel
2014CASESAutomatic custom instruction identification in memory streaming algorithms.Martin Haa, Lars Bauer, Jrg Henkel
2014DACReducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture.Fazal Hameed, Lars Bauer, Jrg Henkel
2014DACMulti-Layer Dependability: From Microarchitecture to Application Level.Jrg Henkel, Lars Bauer, Hongyan Zhang, Semeen Rehman, Muhammad Shafique
2014DACGUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems.Hongyan Zhang, Michael A. Kochte, Michael E. Imhof, Lars Bauer, Hans-Joachim Wunderlich, Jrg Henkel
2014FPGAMORP: makespan optimization for processors with an embedded reconfigurable fabric.Artjom Grudnitsky, Lars Bauer, Jrg Henkel
2013CASESSimultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies.Fazal Hameed, Lars Bauer, Jrg Henkel
2013CASESHardware acceleration for programs in SSA form.Manuel Mohr, Artjom Grudnitsky, Tobias Modschiedler, Lars Bauer, Sebastian Hack, Jrg Henkel
2013DACReliable on-chip systems in the nano-era: lessons learnt and future trends.Jrg Henkel, Lars Bauer, Nikil D. Dutt, Puneet Gupta, Sani R. Nassif, Muhammad Shafique, Mehdi Baradaran Tahoori, Norbert Wehn
2013DATEAdaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores.Fazal Hameed, Lars Bauer, Jrg Henkel
2013DATEAn H.264 Quad-FullHD low-latency intra video encoder.Muhammad Usman Karim Khan, Jan Micha Borrmann, Lars Bauer, Muhammad Shafique, Jrg Henkel
2013ITCModule diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures.Hongyan Zhang, Lars Bauer, Michael A. Kochte, Eric Schneider, Claus Braun, Michael E. Imhof, Hans-Joachim Wunderlich, Jrg Henkel
2012ASPDACInvasive manycore architectures.Jrg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hbner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe
2012DATEPartial online-synthesis for mixed-grained reconfigurable architectures.Artjom Grudnitsky, Lars Bauer, Jrg Henkel
2012DATEDynamic cache management in multi-core architectures through run-time adaptation.Fazal Hameed, Lars Bauer, Jrg Henkel
2012FCCMPATS: A Performance Aware Task Scheduler for Runtime Reconfigurable Processors.Lars Bauer, Artjom Grudnitsky, Muhammad Shafique, Jrg Henkel
2012IOLTSTransparent structural online test for reconfigurable systems.Mohamed Abdelfattah, Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Jrg Henkel, Hans-Joachim Wunderlich
2011DATEmRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions.Waheed Ahmed, Muhammad Shafique, Lars Bauer, Jrg Henkel
2011DATEMinority-Game-based resource allocation for run-time reconfigurable multi-core processors.Muhammad Shafique, Lars Bauer, Waheed Ahmed, Jrg Henkel
2011FCCMRun-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors.Waheed Ahmed, Muhammad Shafique, Lars Bauer, Manuel Hammerich, Jrg Henkel, Jrgen Becker
2010DATEKAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture.Ralf Knig, Lars Bauer, Timo Stripf, Muhammad Shafique, Waheed Ahmed, Jrgen Becker, Jrg Henkel
2010DATEenBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder.Muhammad Shafique, Lars Bauer, Jrg Henkel
2010ICCADSelective instruction set muting for energy-aware adaptive processors.Muhammad Shafique, Lars Bauer, Jrg Henkel
2009DATECross-architectural design space exploration tool for reconfigurable processors.Lars Bauer, Muhammad Shafique, Jrg Henkel
2009DATEA parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec.Muhammad Shafique, Lars Bauer, Jrg Henkel
2009FPLRISPP: A run-time adaptive reconfigurable embedded processor.Lars Bauer, Muhammad Shafique, Jrg Henkel
2009ICCADREMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set.Muhammad Shafique, Lars Bauer, Jrg Henkel
2008DACRun-time instruction set selection in a transmutable embedded processor.Lars Bauer, Muhammad Shafique, Jrg Henkel
2008DATERun-time System for an Extensible Embedded Processor with Dynamic Instruction Set.Lars Bauer, Muhammad Shafique, Stephanie Kreutz, Jrg Henkel
2008FPLA computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor.Lars Bauer, Muhammad Shafique, Jrg Henkel
2008ISLPED3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding.Muhammad Shafique, Lars Bauer, Jrg Henkel
2007DACRISPP: Rotating Instruction Set Processing Platform.Lars Bauer, Muhammad Shafique, Simon Kramer, Jrg Henkel