Marie-Lise Flottes
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
51
Venues
11
Active years
1992–2026
Best venue rank
A*
Where they publish
Papers
51 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ETS | Exploiting Near-Memory Computing Resources for Native, Adaptive, and Low-Overhead MBIST. | Sabrina Ait Belkacem, Lila Ammoura, Maria Ramirez-Corrales, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel |
| 2024 | DATE | A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures. | Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel |
| 2024 | ETS | Power Analysis Attack Against post-SAT Logic Locking schemes. | Nassim Riadi, Florent Bruguier, Pascal Benoit, Sophie Dupuis, Marie-Lise Flottes |
| 2023 | ETS | Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture. | Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel |
| 2022 | CCS | Leveraging Layout-based Effects for Locking Analog ICs. | Muayad J. Aljafar, Florence Azas, Marie-Lise Flottes, Samuel Pagliarini |
| 2022 | ETS | A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing. | S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel |
| 2021 | ETS | A Plug and Play Digital ABIST Controller for Analog Sensors in Secure Devices. | S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel |
| 2021 | IOLTS | High-level Intellectual Property Obfuscation via Decoy Constants. | Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini |
| 2020 | IOLTS | Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. | Florence Azas, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzrho, Laurent Latorre, Franois Lefvre, Bruno Rouzeyre, Emanuele Valea, T. Vayssade, Arnaud Virazel |
| 2020 | IOLTS | A Secure Scan Controller for Protecting Logic Locking. | Quang-Linh Nguyen, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre |
| 2019 | DDECS | Encryption-Based Secure JTAG. | Emanuele Valea, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre |
| 2018 | FDTC | Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model. | Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Stephan De Castro, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hly, Rgis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre |
| 2018 | IOLTS | The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks. | Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hly, Rgis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre |
| 2017 | ETS | Scan chain encryption for the test, diagnosis and debug of secure circuits. | Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Paolo Prinetto, Marco Restifo |
| 2015 | DATE | New testing procedure for finding insertion sites of stealthy hardware trojans. | Sophie Dupuis, Papa-Sidi Ba, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre |
| 2015 | ETS | Session-less based thermal-aware 3D-SIC test scheduling. | Marie-Lise Flottes, Joao Azevedo, Giorgio Di Natale, Bruno Rouzeyre |
| 2014 | IOLTS | A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans. | Sophie Dupuis, Papa-Sidi Ba, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
| 2014 | IOLTS | Customized cell detector for laser-induced-fault detection. | Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
| 2014 | VTS | Built-in self-test for manufacturing TSV defects before bonding. | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche |
| 2013 | DSD | Laser-Induced Fault Simulation. | Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
| 2013 | IOLTS | A smart test controller for scan chains in secure circuits. | Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
| 2012 | ETS | On-chip test comparison for protecting confidential data in secure ICs. | Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
| 2012 | VTS | Are advanced DfT structures sufficient for preventing scan-attacks? | Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
| 2011 | DDECS | Power consumption traces realignment to improve differential power analysis. | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka, Denis Ral |
| 2011 | ETS | Scan Attacks and Countermeasures in Presence of Scan Response Compactors. | Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
| 2010 | DDECS | Ensuring high testability without degrading security: Embedded tutorial on "test and security". | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
| 2010 | ETS | Evaluation of concurrent error detection techniques on the Advanced Encryption Standard. | Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
| 2010 | IOLTS | Evaluation of concurrent error detection techniques on the advanced encryption standard. | Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
| 2008 | ETS | A Reliable Architecture for the Advanced Encryption Standard. | Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre |
| 2008 | ITC | Wireless Test Structure for Integrated Systems. | Ziad Noun, Philippe Cauvet, Marie-Lise Flottes, David Andreu, Serge Bernard |
| 2007 | DDECS | A Novel Parity Bit Scheme for SBox in AES Circuits. | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
| 2007 | IOLTS | An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
| 2006 | DATE | A secure scan design methodology. | David Hly, Frdric Bancel, Marie-Lise Flottes, Bruno Rouzeyre |
| 2006 | IOLTS | Secure Scan Techniques: A Comparison. | David Hly, Frdric Bancel, Marie-Lise Flottes, Bruno Rouzeyre |
| 2005 | DATE | Mutation Sampling Technique for the Generation of Structural Test Data. | Mathieu Scholiv, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre |
| 2005 | ETS | Test control for secure scan designs. | David Hly, Frdric Bancel, Marie-Lise Flottes, Bruno Rouzeyre |
| 2004 | DATE | An Arithmetic Structure for Test Data Horizontal Compression. | Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre |
| 2004 | ETS | User-constrained test architecture design for modular SOC testing. | Ludovic A. Krundel, Sandeep Kumar Goel, Erik Jan Marinissen, Marie-Lise Flottes, Bruno Rouzeyre |
| 2004 | IOLTS | Scan Design and Secure Chip. | David Hly, Marie-Lise Flottes, Frdric Bancel, Bruno Rouzeyre, Nicolas Brard, Michel Renovell |
| 2003 | ETS | An efficient approach to SoC wrapper design, TAM configuration and test scheduling. | Julien Pouget, Erik Larsson, Zebo Peng, Marie-Lise Flottes, Bruno Rouzeyre |
| 2002 | DATE | A Heuristic for Test Scheduling at System Level. | Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre |
| 2000 | ETS | A method for trading off test time, area and fault coverage in datapath BIST synthesis. | David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre |
| 2000 | ISCAS | A controller resynthesis based method for improving datapath testability. | Marie-Lise Flottes, Bruno Rouzeyre, Laurent Volpe |
| 2000 | ITC | BISTing data paths at behavioral level. | David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre |
| 1999 | ETS | Partial set for flip-flops based on state requirement for non-scan BIST scheme. | Marie-Lise Flottes, Christian Landrault, A. Petitqueux |
| 1998 | DATE | Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe |
| 1998 | VTS | Low Cost Partial Scan Design: A High Level Synthesis Approach. | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe |
| 1997 | DATE | Analyzing testability from behavioral to RT level. | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre |
| 1995 | DATE | High-level synthesis for easy testability. | Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre |
| 1995 | ITC | Is High-Level Test Synthesis Just Design for Test? | Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre |
| 1992 | VLSID | A New Reliable Method for Delay-Fault Diagnosis. | Marie-Lise Flottes, Patrick Girard, Christian Landrault, Serge Pravossoudovitch |