| 2017 | ICCAD | An automated SAT-based method for the design of on-chip bit-flip detectors. | Pouya Taatizadeh, Nicola Nicolici |
| 2017 | IOLTS | A generic embedded sequence generator for constrained-random validation with weighted distributions. | Xiaobing Shi, Nicola Nicolici |
| 2016 | ETS | Bit-flip detection-driven selection of trace signals. | Amin Vali, Nicola Nicolici |
| 2015 | DATE | A methodology for automated design of embedded bit-flips detectors in post-silicon validation. | Pouya Taatizadeh, Nicola Nicolici |
| 2015 | ICCAD | On-Chip Generation of Uniformly Distributed Constrained-Random Stimuli for Post-Silicon Validation. | Xiaobing Shi, Nicola Nicolici |
| 2015 | ICCAD | SAT Solving using FPGA-based Heterogeneous Computing. | Jason Thong, Nicola Nicolici |
| 2015 | ICCD | Emulation-based selection and assessment of assertion checkers for post-silicon validation. | Pouya Taatizadeh, Nicola Nicolici |
| 2014 | ITC | On-chip constrained random stimuli generation for post-silicon validation using compact masks. | Xiaobing Shi, Nicola Nicolici |
| 2013 | DAC | Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation. | Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici |
| 2013 | ICCAD | FPGA acceleration of enhanced boolean constraint propagation for SAT solvers. | Jason Thong, Nicola Nicolici |
| 2012 | ASPDAC | Automated data analysis techniques for a modern silicon debug environment. | Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita |
| 2012 | ITC | In-system constrained-random stimuli generation for post-silicon validation. | Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici |
| 2011 | DAC | Dynamic binary translation to a reconfigurable target for on-the-fly acceleration. | Phillip Kinsman, Nicola Nicolici |
| 2011 | ICCAD | In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation. | Zahra Lak, Nicola Nicolici |
| 2010 | DAC | Embedded memory binding in FPGAs. | Kaveh Elizeh, Nicola Nicolici |
| 2010 | DAC | Robust design methods for hardware accelerators for iterative algorithms in scientific computing. | Adam B. Kinsman, Nicola Nicolici |
| 2010 | DAC | Post-silicon validation opportunities, challenges and recent advances. | Subhasish Mitra, Sanjit A. Seshia, Nicola Nicolici |
| 2010 | DAC | A novel optimal single constant multiplication algorithm. | Jason Thong, Nicola Nicolici |
| 2010 | ETS | Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging. | Ho Fai Ko, Nicola Nicolici |
| 2010 | FPGA | Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture. | Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici |
| 2010 | ICCD | Combined optimal and heuristic approaches for multiple constant multiplication. | Jason Thong, Nicola Nicolici |
| 2010 | ITC | Automated trace signals selection using the RTL descriptions. | Ho Fai Ko, Nicola Nicolici |
| 2009 | DATE | Finite Precision bit-width allocation using SAT-Modulo Theory. | Adam B. Kinsman, Nicola Nicolici |
| 2009 | DATE | Automated data analysis solutions to silicon debug. | Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris |
| 2009 | ETS | Resource-Efficient Programmable Trigger Units for Post-Silicon Validation. | Ho Fai Ko, Nicola Nicolici |
| 2009 | ICCD | Computational bit-width allocation for operations in vector calculus. | Adam B. Kinsman, Nicola Nicolici |
| 2008 | DATE | Power-Aware Testing and Test Strategies for Low Power Devices. | Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen |
| 2008 | DATE | Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation. | Ho Fai Ko, Nicola Nicolici |
| 2008 | DATE | On Automated Trigger Event Generation in Post-Silicon Validation. | Ho Fai Ko, Nicola Nicolici |
| 2008 | ETS | On Bypassing Blocking Bugs during Post-Silicon Validation. | Ehab Anis Daoud, Nicola Nicolici |
| 2008 | IROS | Hardware-based parallel computing for real-time haptic rendering of deformable objects. | Ramin Mafi, Shahin Sirouspour, Brian Moody, Behzad Mahdavikhah, Kaveh Elizeh, Adam B. Kinsman, Nicola Nicolici, Mahyar Fotoohi, D. Madill |
| 2008 | ITC | Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs. | Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici |
| 2007 | DATE | Interactive presentation: Low cost debug architecture using lossy compression for silicon debug. | Ehab Anis, Nicola Nicolici |
| 2007 | ETS | Embedded Tutorial on Low Power Test. | Nicola Nicolici, Xiaoqing Wen |
| 2007 | ITC | On using lossless compression of debug data in embedded logic analysis. | Ehab Anis, Nicola Nicolici |
| 2006 | ICCD | RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. | Ho Fai Ko, Nicola Nicolici |
| 2005 | ASPDAC | Register-transfer level functional scan for hierarchical designs. | Ho Fai Ko, Qiang Xu, Nicola Nicolici |
| 2005 | DAC | Multi-frequency wrapper design and optimization for embedded cores under average power constraints. | Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty |
| 2005 | ETS | Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels. | Adam B. Kinsman, Nicola Nicolici |
| 2005 | ITC | On concurrent test of wrapped cores and unwrapped logic blocks in SOCs. | Qiang Xu, Nicola Nicolici |
| 2004 | DATE | Wrapper Design for Testing IP Cores with Multiple Clock Domains. | Qiang Xu, Nicola Nicolici |
| 2004 | ICCD | Functional Illinois Scan Design at RTL. | Ho Fai Ko, Nicola Nicolici |
| 2004 | ICCD | Compressed Embedded Diagnosis of Logic Cores. | Scott Ollivierre, Adam B. Kinsman, Nicola Nicolici |
| 2004 | ITC | Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores. | Qiang Xu, Nicola Nicolici |
| 2003 | DATE | Test Data Compression: The System Integrator's Perspective. | Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici |
| 2003 | DATE | Delay Fault Testing of Core-Based Systems-on-a-Chi. | Qiang Xu, Nicola Nicolici |
| 2003 | ICCAD | Hardware/Software Co-testing of Embedded Memories in Complex SOCs. | Bai Hong Fang, Qiang Xu, Nicola Nicolici |
| 2003 | ITC | On Reducing Wrapper Boundary Register Cells in Modular SOC Testing. | Qiang Xu, Nicola Nicolici |
| 2002 | DATE | Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression. | Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici |
| 2002 | ICCD | Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding. | Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici |
| 2002 | ITC | Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing. | Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici |
| 2002 | VTS | Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions. | Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici |
| 2001 | DATE | Testability trade-offs for BIST RTL data paths: the case for three dimensional design space. | Nicola Nicolici, Bashir M. Al-Hashimi |
| 2001 | ISCAS | Power constrained test scheduling using power profile manipulation. | Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici |
| 2001 | ITC | Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation. | Nicola Nicolici, Bashir M. Al-Hashimi |
| 2000 | DATE | Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits. | Nicola Nicolici, Bashir M. Al-Hashimi |
| 2000 | ITC | Power conscious test synthesis and scheduling for BIST RTL data paths. | Nicola Nicolici, Bashir M. Al-Hashimi |
| 1999 | DATE | Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths. | Nicola Nicolici, Bashir M. Al-Hashimi |