| 2026 | DATE | A Reinforcement Learning Framework for Good Die in Bad Neighborhood Analysis. | Mohammad Ershad Shaik, Abhishek Kumar Mishra, Nagarajan Kandasamy, Nur A. Touba |
| 2024 | IOLTS | Double Adjacent Error Correction in RRAM Matrix Multiplication using Weighted Checksums. | Kenrick Xavier Pinto, Krishnaja Kodali, Abhishek Das, Nur A. Touba |
| 2024 | VTS | WaferCap: Open Classification of Wafer Map Patterns using Deep Capsule Network. | Abhishek Kumar Mishra, Mohammad Ershad Shaik, Anush Niranjan Lingamoorthy, Suman Kumar, Anup Das, Nagarajan Kandasamy, Nur A. Touba |
| 2020 | VTS | Selective Checksum based On-line Error Correction for RRAM based Matrix Operations. | Abhishek Das, Nur A. Touba |
| 2019 | VTS | A Graph Theory Approach towards IJTAG Security via Controlled Scan Chain Isolation. | Abhishek Das, Nur A. Touba |
| 2019 | VTS | Layered-ECC: A Class of Double Error Correcting Codes for High Density Memory Systems. | Abhishek Das, Nur A. Touba |
| 2018 | VTS | Systematic b-adjacent symbol error correcting reed-solomon codes with parallel decoding. | Abhishek Das, Nur A. Touba |
| 2017 | ICCD | Limited Magnitude Error Correction Using OLS Codes for Memories with Multilevel Cells. | Abhishek Das, Nur A. Touba |
| 2016 | DAC | Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning. | Jin-Hyun Kang, Nur A. Touba, Joon-Sung Yang |
| 2016 | ITC | Using symbolic canceling to improve diagnosis from compacted response. | Kamran Saleem, Nur A. Touba |
| 2014 | ITC | Improving test compression with scan feedforward techniques. | Sreenivaas S. Muthyala, Nur A. Touba |
| 2013 | VTS | SOC test compression scheme using sequential linear decompressors with retained free variables. | Sreenivaas S. Muthyala, Nur A. Touba |
| 2012 | ITC | Improving test compression by retaining non-pivot free variables in sequential linear decompressors. | Sreenivaas S. Muthyala, Nur A. Touba |
| 2012 | VTS | Exploiting X-correlation in output compression via superset X-canceling. | Jinsuk Chung, Nur A. Touba |
| 2011 | VTS | Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories. | Rudrajit Datta, Nur A. Touba |
| 2010 | ITC | Post-manufacturing ECC customization based on Orthogonal Latin Square codes and its application to ultra-low power caches. | Rudrajit Datta, Nur A. Touba |
| 2010 | VTS | CSER: BISER-based concurrent soft-error resilience. | Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li |
| 2009 | ITC | Test point insertion using functional flip-flops to drive control points. | Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba |
| 2009 | ITC | An industrial case study for X-canceling MISR. | Joon-Sung Yang, Nur A. Touba, Shih-Yu Yang, T. M. Mak |
| 2009 | VTS | Exploiting Unused Spare Columns to Improve Memory ECC. | Rudrajit Datta, Nur A. Touba |
| 2009 | VTS | Automated Selection of Signals to Observe for Efficient Silicon Debug. | Joon-Sung Yang, Nur A. Touba |
| 2008 | VTS | Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation. | Ritesh Garg, Richard Putman, Nur A. Touba |
| 2008 | VTS | Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture. | Joon-Sung Yang, Nur A. Touba |
| 2007 | ITC | X-canceling MISR - An X-tolerant methodology for compacting output responses with unknowns using a MISR. | Nur A. Touba |
| 2007 | VTS | Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code. | Avijit Dutta, Nur A. Touba |
| 2007 | VTS | Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression. | Richard Putman, Nur A. Touba |
| 2006 | ITC | Using Limited Dependence Sequential Expansion for Decompressing Test Vectors. | Avijit Dutta, Nur A. Touba |
| 2006 | VTS | Iterative OPDD Based Signal Probability Calculation. | Avijit Dutta, Nur A. Touba |
| 2006 | VTS | Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding. | Jinkyu Lee, Nur A. Touba |
| 2005 | DATE | Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination. | Kedarnath J. Balakrishnan, Nur A. Touba |
| 2005 | ITC | Synthesis of nonintrusive concurrent error detection using an even error detecting function. | Avijit Dutta, Nur A. Touba |
| 2005 | ITC | Methods for improving test compression. | Nur A. Touba |
| 2005 | VTS | Synthesis of Low Power CED Circuits Based on Parity Codes. | Shalini Ghosh, Sugato Basu, Nur A. Touba |
| 2004 | ETS | Relating entropy theory to test data compression. | Kedarnath J. Balakrishnan, Nur A. Touba |
| 2004 | ICCD | Low Power Test Data Compression Based on LFSR Reseeding. | Jinkyu Lee, Nur A. Touba |
| 2004 | ITC | Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion. | Kedarnath J. Balakrishnan, Nur A. Touba |
| 2004 | ITC | Reducing Power Consumption in Memory ECC Checkers. | Shalini Ghosh, Nur A. Touba, Sugato Basu |
| 2004 | VTS | 3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme. | C. V. Krishna, Nur A. Touba |
| 2003 | ICCAD | Adjustable Width Linear Combinational Scan Vector Decompression. | C. V. Krishna, Nur A. Touba |
| 2003 | IOLTS | Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits. | Kartik Mohanram, Egor S. Sogomonyan, Michael Gssel, Nur A. Touba |
| 2003 | ITC | Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. | Kartik Mohanram, Nur A. Touba |
| 2003 | VTS | Deterministic Test Vector Decompression in Software Using Linear Operations. | Kedarnath J. Balakrishnan, Nur A. Touba |
| 2003 | VTS | Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. | Kartik Mohanram, Nur A. Touba |
| 2002 | ISCAS | A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL. | Kartik Mohanram, C. V. Krishna, Nur A. Touba |
| 2002 | ITC | Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression. | C. V. Krishna, Nur A. Touba |
| 2002 | VTS | Very Low Voltage Testing of SOI Integrated Circuits. | Eric W. MacDonald, Nur A. Touba |
| 2002 | VTS | Controlling Peak Power During Scan Testing. | Ranganathan Sankaralingam, Nur A. Touba |
| 2001 | ITC | Test vector encoding using partial LFSR reseeding. | C. V. Krishna, Abhijit Jas, Nur A. Touba |
| 2001 | VTS | Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme. | Abhijit Jas, C. V. Krishna, Nur A. Touba |
| 2001 | VTS | Reducing Power Dissipation during Test Using Scan Chain Disable. | Ranganathan Sankaralingam, Nur A. Touba, Bahram Pouya |
| 2000 | IOLTS | Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes. | Debaleena Das, Nur A. Touba, Markus Seuring, Michael Gssel |
| 2000 | ITC | Reducing test data volume using external/LBIST hybrid test patterns. | Debaleena Das, Nur A. Touba |
| 2000 | VTS | A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains. | Jayabrata Ghosh-Dastidar, Nur A. Touba |
| 2000 | VTS | Virtual Scan Chains: A Means for Reducing Scan Length in Cores. | Abhijit Jas, Bahram Pouya, Nur A. Touba |
| 2000 | VTS | Static Compaction Techniques to Control Scan Vector Power Dissipation. | Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba |
| 1999 | ICCD | Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. | Abhijit Jas, Nur A. Touba |
| 1999 | ISCAS | Observing test response of embedded cores through surrounding logic. | P. K. Jaini, Nur A. Touba |
| 1999 | ISCAS | Configuration self-test in FPGA-based reconfigurable systems. | W. Quddus, Abhijit Jas, Nur A. Touba |
| 1999 | ITC | Fault diagnosis in scan-based BIST using both time and space information. | Jayabrata Ghosh-Dastidar, Debaleena Das, Nur A. Touba |
| 1999 | ITC | Delay testing of SOI circuits: Challenges with the history effect. | Eric W. MacDonald, Nur A. Touba |
| 1999 | VLSID | A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems. | Debaleena Das, Nur A. Touba |
| 1999 | VTS | Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits. | Debaleena Das, Nur A. Touba |
| 1999 | VTS | Adaptive Techniques for Improving Delay Fault Diagnosis. | Jayabrata Ghosh-Dastidar, Nur A. Touba |
| 1999 | VTS | Scan Vector Compression/Decompression Using Statistical Coding. | Abhijit Jas, Jayabrata Ghosh-Dastidar, Nur A. Touba |
| 1998 | ITC | Test vector decompression via cyclical scan chains and its application to testing core-based designs. | Abhijit Jas, Nur A. Touba |
| 1998 | ITC | BETSY: synthesizing circuits for a specified BIST environment. | Zhe Zhao, Bahram Pouya, Nur A. Touba |
| 1998 | VTS | Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes. | Debaleena Das, Nur A. Touba |
| 1998 | VTS | Synthesis of Zero-Aliasing Elementary-Tree Space Compactors. | Bahram Pouya, Nur A. Touba |
| 1997 | ICCD | Pseudo-Random Pattern Testing of Bridging Faults. | Nur A. Touba, Edward J. McCluskey |
| 1997 | ITC | Modifying User-Defined Logic for Test Access to Embedded Cores. | Bahram Pouya, Nur A. Touba |
| 1997 | VTS | Obtaining High Fault Coverage with Circular BIST Via State Skipping. | Nur A. Touba |
| 1997 | VTS | Testing Embedded Cores Using Partial Isolation Rings. | Nur A. Touba, Bahram Pouya |
| 1996 | ITC | Altering a Pseudo-Random Bit Sequence for Scan-Based BIST. | Nur A. Touba, Edward J. McCluskey |
| 1996 | VTS | Test point insertion based on path tracing. | Nur A. Touba, Edward J. McCluskey |
| 1996 | VTS | Applying two-pattern tests using scan-mapping. | Nur A. Touba, Edward J. McCluskey |
| 1995 | ITC | Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST. | Nur A. Touba, Edward J. McCluskey |
| 1995 | VTS | Transformed pseudo-random patterns for BIST. | Nur A. Touba, Edward J. McCluskey |
| 1994 | ICCAD | Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. | Nur A. Touba, Edward J. McCluskey |
| 1994 | ITC | Automated Logic Synthesis of Random-Pattern-Testable Circuits. | Nur A. Touba, Edward J. McCluskey |