| 2026 | ISPASS | Characterizing and Optimizing Cache Placement for Secure Memory Metadata. | Samuel Thomas, Blake Cragen, R. Iris Bahar, Tamara Silbergleit Lehman |
| 2025 | ICRA | Robot Planning Under Uncertainty for Object Assembly and Troubleshooting Using Human Causal Models. | Semanti Basu, Semir Tatlidil, Moon Hwan Kim, Tiffany Tran, Serena Saxena, Tom Williams, Steven A. Sloman, R. Iris Bahar |
| 2024 | ASPLOS | A Midsummer Night's Tree: Efficient and High Performance Secure SCM. | Samuel Thomas, Kidus Workneh, Jac McCarty, Joseph Izraelevitz, Tamara Lehman, R. Iris Bahar |
| 2024 | DAC | Invited: Using Causal Information to Enable More Efficient Robot Operation. | Semanti Basu, Semir Tatlidil, Moon Hwan Kim, Steven A. Sloman, R. Iris Bahar |
| 2022 | ICCAD | A Reconfigurable Hardware Library for Robot Scene Perception. | Yanqi Liu, Anthony Opipari, Odest Chadwicke Jenkins, R. Iris Bahar |
| 2022 | SPAA | HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing Architectures. | Jiwon Choe, Andrew Crotty, Tali Moreshet, Maurice Herlihy, R. Iris Bahar |
| 2021 | ITC | Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits. | Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, R. Iris Bahar |
| 2020 | ICCAD | Hardware Acceleration of Robot Scene Perception Algorithms. | Yanqi Liu, Can Eren Derman, Giuseppe Calderoni, R. Iris Bahar |
| 2019 | DATE | IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM. | Dimitra Papagiannopoulou, Sungseob Whang, Tali Moreshet, R. Iris Bahar |
| 2019 | IROS | GRIP: Generative Robust Inference and Perception for Semantic Robot Manipulation in Adversarial Environments. | Xiaotong Chen, Rui Chen, Zhiqiang Sui, Zhefan Ye, Yanqi Liu, R. Iris Bahar, Odest Chadwicke Jenkins |
| 2019 | VTS | Special Session: Does Approximation Make Testing Harder (or Easier)? | R. Iris Bahar, Ulya R. Karpuzcu, Sasa Misailovic |
| 2019 | SPAA | Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation. | Jiwon Choe, Amy Huang, Tali Moreshet, Maurice Herlihy, R. Iris Bahar |
| 2018 | ICCAD | Robust object estimation using generative-discriminative inference for secure robotics applications. | Yanqi Liu, Alessandro Costantini, R. Iris Bahar, Zhiqiang Sui, Zhefan Ye, Shiyang Lu, Odest Chadwicke Jenkins |
| 2017 | DAC | Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. | Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda |
| 2017 | DATE | Understanding the impact of precision quantization on the accuracy and energy of neural networks. | Soheil Hashemi, Nicholas Anthony, Hokchhay Tann, R. Iris Bahar, Sherief Reda |
| 2016 | CASES | Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems. | Thomas Carle, Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Maurice Herlihy, R. Iris Bahar |
| 2016 | DAC | A fast simulator for the analysis of sub-threshold thermal noise transients. | Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky |
| 2016 | DAC | A low-power dynamic divider for approximate applications. | Soheil Hashemi, R. Iris Bahar, Sherief Reda |
| 2016 | FPL | Hardware acceleration of feature detection and description algorithms on low-power embedded platforms. | Onur Ulusel, Christopher B. Picardo, Christopher B. Harris, Sherief Reda, R. Iris Bahar |
| 2015 | ICCAD | DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications. | Soheil Hashemi, R. Iris Bahar, Sherief Reda |
| 2014 | DATE | ABACUS: A technique for automated behavioral synthesis of approximate computing circuits. | Kumud Nepal, Yueting Li, R. Iris Bahar, Sherief Reda |
| 2013 | ISCA | Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs. | Dimitra Papagiannopoulou, R. Iris Bahar, Tali Moreshet, Maurice Herlihy, Andrea Marongiu, Luca Benini |
| 2012 | FCCM | Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators. | Kumud Nepal, Onur Ulusel, R. Iris Bahar, Sherief Reda |
| 2011 | ETS | Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. | Nuno Alves, Yiwen Shi, Nicholas Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar |
| 2011 | VTS | Enhancing online error detection through area-efficient multi-site implications. | Nuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar, Kundan Nepal |
| 2009 | DATE | Detecting errors using multi-cycle invariance information. | Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar |
| 2009 | FPGA | High-performance, cost-effective heterogeneous 3D FPGA architectures. | Roto Le, Sherief Reda, R. Iris Bahar |
| 2009 | ICCAD | Compacting test vector sets via strategic use of implications. | Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan Nepal |
| 2009 | ISLPED | Reducing the leakage and timing variability of 2D ICcs using 3D ICs. | Sherief Reda, Aung Si, R. Iris Bahar |
| 2009 | ITC | AutoRex: An automated post-silicon clock tuning tool. | Desta Tadesse, Joel Grodstein, R. Iris Bahar |
| 2008 | ISLPED | Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. | Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino |
| 2008 | ITC | Using Implications for Online Error Detection. | Kundan Nepal, Nuno Alves, Jennifer Dworak, R. Iris Bahar |
| 2008 | VTS | Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. | Desta Tadesse, R. Iris Bahar, Joel Grodstein |
| 2007 | DATE | Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. | Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky |
| 2007 | DATE | Accurate timing analysis using SAT and pattern-dependent delay models. | Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein |
| 2007 | ICCAD | Strategies for improving the parametric yield and profits of 3D ICs. | Cesare Ferri, Sherief Reda, R. Iris Bahar |
| 2006 | DAC | A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors. | Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss |
| 2006 | DATE | Designing MRF based error correcting circuits for memory elements. | Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky |
| 2006 | ICCD | Trends and Future Directions in Nano Structure Based Computing and Fabrication. | R. Iris Bahar |
| 2006 | SPAA | Energy implications of multiprocessor synchronization. | Tali Moreshet, R. Iris Bahar, Maurice Herlihy |
| 2005 | DAC | Designing logic circuits for probabilistic computation in the presence of noise. | Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky |
| 2005 | ISLPED | Energy reduction in multiprocessor systems using transactional memory. | Tali Moreshet, R. Iris Bahar, Maurice Herlihy |
| 2004 | ICCD | Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm. | Yu Bai, R. Iris Bahar |
| 2004 | ICCD | Fetch Halting on Critical Load Misses. | Nikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss |
| 2003 | DAC | Power-aware issue queue design for speculative instructions. | Tali Moreshet, R. Iris Bahar |
| 2003 | ICCAD | A Probabilistic-Based Design Methodology for Nanoscale Computation. | R. Iris Bahar, Joseph L. Mundy, Jie Chen |
| 2003 | ICCD | Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. | Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein |
| 2001 | ISCA | Power and energy reduction via pipeline balancing. | R. Iris Bahar, Srilatha Manne |
| 1999 | ICCD | The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency. | Brian R. Fisk, R. Iris Bahar |
| 1998 | ISLPED | Power and performance tradeoffs using various caching strategies. | R. Iris Bahar, Gianluca Albera, Srilatha Manne |
| 1996 | ISLPED | Symbolic computation of logic implications for technology-dependent low-power synthesis. | R. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi |
| 1995 | DAC | Computing the Maximum Power Cycles of a Sequential Circuit. | Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino |
| 1995 | ICCAD | Boolean techniques for low power driven re-synthesis. | R. Iris Bahar, Fabio Somenzi |
| 1995 | ISLPED | CMOS dynamic power estimation based on collapsible current source transistor modeling. | Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi |
| 1994 | ICCAD | A symbolic method to reduce power consumption of circuits containing false paths. | R. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi |
| 1993 | ICCAD | Algebraic decision diagrams and their applications. | R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi |