| 2025 | ASPDAC | Exploring Better Intra-Cell Routability for Layout Synthesis of Multi-Row Standard Cells. | Kairong Guo, Xiaohan Gao, Haoyi Zhang, Runsheng Wang, Ru Huang, Yibo Lin |
| 2025 | DAC | EdgeMM: Multi-Core CPU with Heterogeneous AI-Extension and Activation-aware Weight Pruning for Multimodal LLMs at Edge. | Kangbo Bai, Le Ye, Ru Huang, Tianyu Jia |
| 2025 | DAC | DuQTTA: Dual Quantized Tensor-Train Adaptation with Decoupling Magnitude-Direction for Efficient Fine-Tuning of LLMs. | Haoyan Dong, Hai-Bao Chen, Jingjing Chang, Yixin Yang, Ziyang Gao, Zhigang Ji, Runsheng Wang, Ru Huang |
| 2025 | DAC | A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis. | Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin |
| 2025 | DAC | Local-GS: An Order-Independent Gaussian Splatting Training Accelerator Exploiting Splat Locality. | Yiyang Sun, Qinzhe Zhi, Yiqi Jing, Le Ye, Ru Huang, Tianyu Jia |
| 2025 | DAC | SpecASR: Accelerating LLM-based Automatic Speech Recognition via Speculative Decoding. | Linye Wei, Shuzhang Zhong, Songqiang Xu, Runsheng Wang, Ru Huang, Meng Li |
| 2025 | DAC | ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance. | Tong Xie, Jiawang Zhao, Zishen Wan, Zuodong Zhang, Yuan Wang, Runsheng Wang, Ru Huang, Meng Li |
| 2025 | DAC | UniCAIM: A Unified CAM/CIM Architecture with Static-Dynamic KV Cache Pruning for Efficient Long-Context LLM Inference. | Weikai Xu, Wenxuan Zeng, Qianqian Huang, Meng Li, Ru Huang |
| 2025 | DAC | 3D-TokSIM: Stacking 3D Memory with Token-Stationary Compute-in-Memory for Speculative LLM Inference. | Wentao Zhao, Boya Lv, Meng Wu, Peiyu Chen, Fengyun Yan, Yufei Ma, Tianyu Jia, Ru Huang, Le Ye |
| 2025 | DAC | HybriMoE: Hybrid CPU-GPU Scheduling and Cache Management for Efficient MoE Inference. | Shuzhang Zhong, Yanfan Sun, Ling Liang, Runsheng Wang, Ru Huang, Meng Li |
| 2025 | DATE | A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-Sided Signals. | Haoran Lu, Xun Jiang, Yanbang Chu, Ziqiao Xu, Rui Guo, Wanyue Peng, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang |
| 2025 | DATE | Handling Latch Loops in Timing Analysis with Improved Complexity and Divergent Loop Detection. | Xizhe Shi, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang |
| 2025 | DATE | SCALES: Boost Binary Neural Network for Image Super-Resolution with Efficient Scalings. | Renjie Wei, Zechun Liu, Yuchen Fan, Runsheng Wang, Ru Huang, Meng Li |
| 2025 | DATE | Compact Non-Volatile Lookup Table Architecture Based on Ferroelectric FET Array Through In-Situ Combinatorial One-Hot Encoding for Reconfigurable Computing. | Weikai Xu, Meng Li, Qianqian Huang, Ru Huang |
| 2025 | DATE | FLASH: An Efficient Hardware Accelerator Leveraging Approximate and Sparse FFT for Homomorphic Encryption. | Tengyu Zhang, Yufei Xue, Ling Liang, Zhen Gu, Yuan Wang, Runsheng Wang, Ru Huang, Meng Li |
| 2025 | DATE | Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUs. | Zhantong Zhu, Hongou Li, Wenjie Ren, Meng Wu, Le Ye, Ru Huang, Tianyu Jia |
| 2025 | DATE | MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D IC. | Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Ru Huang |
| 2025 | ICCV | Entropy-Adaptive Diffusion Policy Optimization with Dynamic Step Alignment. | Renye Yan, Jikang Cheng, Yaozhong Gan, Shikun Sun, You Wu, Yunfan Yang, Ling Liang, Jinlong Lin, Yeshuang Zhu, Jie Zhou, Jinchao Zhang, Junliang Xing, Yimao Cai, Ru Huang |
| 2025 | ISCAS | SA-CIM: A 28nm 16Mb RRAM-based Sparsity-Aware Compute-In-Memory Macro for Edge AI Algorithm Processing. | Hao Ding, Zongwei Wang, Jinshan Li, Shigeng Zhao, Heting Gao, Junbo Ao, Ling Liang, Yimao Cai, Ru Huang |
| 2025 | ISCAS | HRC-CIM: Hybrid RRAM-Capacitor Cell based Compute-in-Memory with High Linearity, Parallelism and Energy Efficiency. | Jinshan Li, Zongwei Wang, Hao Ding, Yunfan Yang, Shigeng Zhao, Shengyu Bao, Jingwei Sun, Ruiqing Xie, Zhuoya Chen, Yimao Cai, Ru Huang |
| 2025 | ISCAS | LayoutCopilot: LLM-Empowered Analog Layout Design towards Enhanced Human-Machine Interaction. | Bingyang Liu, Haoyi Zhang, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang |
| 2024 | DAC | An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology. | Zhiyuan Chen, Yufei Ma, Keyi Li, Yifan Jia, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, Ru Huang |
| 2024 | DAC | PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning. | Yufan Du, Zizheng Guo, Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang |
| 2024 | DAC | AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration. | Yiqi Jing, Meng Wu, Jiaqi Zhou, Yiyang Sun, Yufei Ma, Ru Huang, Tianyu Jia, Le Ye |
| 2024 | DAC | FastQuery: Communication-efficient Embedding Table Query for Private LLMs inference. | Chenqi Lin, Tianshi Xu, Zebin Yang, Runsheng Wang, Ru Huang, Meng Li |
| 2024 | DAC | Compact and Efficient CAM Architecture through Combinatorial Encoding and Self-Terminating Searching for In-Memory-Searching Accelerator. | Weikai Xu, Jin Luo, Qianqian Huang, Ru Huang |
| 2024 | DAC | EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration. | Haoyi Zhang, Jiahao Song, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang |
| 2024 | DATE | Heterogeneous Static Timing Analysis with Advanced Delay Calculator. | Zizheng Guo, Tsung-Wei Huang, Zhou Jin, Cheng Zhuo, Yibo Lin, Runsheng Wang, Ru Huang |
| 2024 | DATE | BlockAMC: Scalable In-Memory Analog Matrix Computing for Solving Linear Systems. | Lunshuai Pan, Pushen Zuo, Yubiao Luo, Zhong Sun, Ru Huang |
| 2024 | DATE | IMCE: An In-Memory Computing and Encrypting Hardware Architecture for Robust Edge Security. | Hanyong Shao, Boyi Fu, Jinghao Yang, Wenpu Luo, Chang Su, Zhiyuan Fu, Kechao Tang, Ru Huang |
| 2024 | DATE | ASCEND: Accurate yet Efficient End-to-End Stochastic Computing Acceleration of Vision Transformer. | Tong Xie, Yixuan Hu, Renjie Wei, Meng Li, Yuan Wang, Runsheng Wang, Ru Huang |
| 2024 | DATE | SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios. | Haoyi Zhang, Xiaohan Gao, Zilong Shen, Jiahao Song, Xiaoxu Cheng, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang |
| 2024 | ICCAD | Hierarchical Power Co-Optimization and Management for LLM Chiplet Designs. | Yanchi Dong, Xueping Liu, Xiaochen Hao, Yun Liang, Ru Huang, Le Ye, Tianyu Jia |
| 2024 | ICCAD | Fusion of Global Placement and Gate Sizing with Differentiable Optimization. | Yufan Du, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang |
| 2024 | ICCAD | Joint Placement Optimization for Hierarchical Analog/Mixed-Signal Circuits. | Xiaohan Gao, Haoyi Zhang, Bingyang Liu, Yibo Lin, Runsheng Wang, Ru Huang |
| 2024 | ICCAD | HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis. | Zizheng Guo, Zuodong Zhang, Wuxi Li, Tsung-Wei Huang, Xizhe Shi, Yufan Du, Yibo Lin, Runsheng Wang, Ru Huang |
| 2024 | ICCAD | OSCA: End-to-end Serial Stochastic Computing Neural Acceleration with Fine-grained Scaling and Piecewise Activation. | Yixuan Hu, Yikang Jia, Meng Li, Yuan Wang, Runsheng Wang, Ru Huang |
| 2024 | ICCAD | MORPH: More Robust ASIC Placement for Hybrid Region Constraint Management. | Jing Mai, Zuodong Zhang, Yibo Lin, Runsheng Wang, Ru Huang |
| 2024 | ICCAD | ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC. | Qipan Wang, Xueqing Li, Tianyu Jia, Yibo Lin, Runsheng Wang, Ru Huang |
| 2024 | ICCAD | MCUBERT: Memory-Efficient BERT Inference on Commodity Microcontrollers. | Zebin Yang, Renze Chen, Taiqiang Wu, Ngai Wong, Yun Liang, Runsheng Wang, Ru Huang, Meng Li |
| 2024 | ICCAD | Enforcing hard constraints in physics-informed learning for transient TSV electromigration analysis. | Xiaoman Yang, Hai-Bao Chen, Wenjie Zhu, Yuhan Zhang, Yongkang Xue, Pengpeng Ren, Runsheng Wang, Zhigang Ji, Ru Huang |
| 2024 | ICCAD | FlexHE: A flexible Kernel Generation Framework for Homomorphic Encryption-Based Private Inference. | Jiangrui Yu, Wenxuan Zeng, Tianshi Xu, Renze Chen, Yun Liang, Runsheng Wang, Ru Huang, Meng Li |
| 2024 | ICCAD | AdapMoE: Adaptive Sensitivity-based Expert Gating and Management for Efficient MoE Inference. | Shuzhang Zhong, Ling Liang, Yuan Wang, Runsheng Wang, Ru Huang, Meng Li |
| 2024 | ICCAD | ProPD: Dynamic Token Tree Pruning and Generation for LLM Parallel Decoding. | Shuzhang Zhong, Zebin Yang, Ruihao Gong, Runsheng Wang, Ru Huang, Meng Li |
| 2024 | ICCAD | FaStTherm: Fast and Stable Full-Chip Transient Thermal Predictor Considering Nonlinear Effects. | Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Ru Huang |
| 2024 | ICLR | CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment. | Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang |
| 2024 | ISCAS | FS-BAND: A Frequency-Sensitive Banding Detector. | Zijian Chen, Wei Sun, Zicheng Zhang, Ru Huang, Fangfang Lu, Xiongkuo Min, Guangtao Zhai, Wen-Jun Zhang |
| 2024 | MICRO | Hestia: An Efficient Cross-Level Debugger for High-Level Synthesis. | Ruifan Xu, Jin Luo, Yawen Zhang, Yibo Lin, Runsheng Wang, Ru Huang, Yun Liang |
| 2023 | ASPDAC | RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation. | Peiyu Chen, Meng Wu, Yufei Ma, Le Ye, Ru Huang |
| 2023 | DAC | A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware. | Yanchi Dong, Tianyu Jia, Kaixuan Du, Yiqi Jing, Qijun Wang, Pixian Zhan, Yadong Zhang, Fengyun Yan, Yufei Ma, Yun Liang, Le Ye, Ru Huang |
| 2023 | DAC | General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism. | Zizheng Guo, Zuodong Zhang, Xun Jiang, Wuxi Li, Yibo Lin, Runsheng Wang, Ru Huang |
| 2023 | DAC | Efficient Non-Linear Adder for Stochastic Computing with Approximate Spatial-Temporal Sorting Network. | Yixuan Hu, Tengyu Zhang, Meng Li, Renjie Wei, Liangzhen Lai, Yuan Wang, Runsheng Wang, Ru Huang |
| 2023 | DAC | MTL-Designer: An Integrated Flow for Analysis and Synthesis of Microstrip Transmission Line. | Qipan Wang, Ping Liu, Liguo Jiang, Mingjie Liu, Yibo Lin, Runsheng Wang, Ru Huang |
| 2023 | DATE | Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion. | Yixuan Hu, Tengyu Zhang, Renjie Wei, Meng Li, Runsheng Wang, Yuan Wang, Ru Huang |
| 2023 | DATE | SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility. | Haoyi Zhang, Xiaohan Gao, Haoyang Luo, Jiahao Song, Xiyuan Tang, Junhua Liu, Yibo Lin, Runsheng Wang, Ru Huang |
| 2023 | DATE | READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction. | Zuodong Zhang, Meng Li, Yibo Lin, Runsheng Wang, Ru Huang |
| 2023 | ICCAD | Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms. | Xun Jiang, Zizheng Guo, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang |
| 2023 | ICCAD | Falcon: Accelerating Homomorphically Encrypted Convolutions for Efficient Private Mobile Network Inference. | Tianshi Xu, Meng Li, Runsheng Wang, Ru Huang |
| 2023 | ICCAD | READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction. | Zuodong Zhang, Renjie Wei, Meng Li, Yibo Lin, Runsheng Wang, Ru Huang |
| 2023 | ICCAD | Memory-aware Scheduling for Complex Wired Networks with Iterative Graph Optimization. | Shuzhang Zhong, Meng Li, Yun Liang, Runsheng Wang, Ru Huang |
| 2023 | ICCV | MPCViT: Searching for Accurate and Efficient MPC-Friendly Vision Transformer with Heterogeneous Attention. | Wenxuan Zeng, Meng Li, Wenjie Xiong, Tong Tong, Wen-Jie Lu, Jin Tan, Runsheng Wang, Ru Huang |
| 2023 | MICRO | Khronos: Fusing Memory Access for Improved Hardware RTL Simulation. | Kexing Zhou, Yun Liang, Yibo Lin, Runsheng Wang, Ru Huang |
| 2022 | ASPDAC | Heterogeneous Memory Architecture Accommodating Processing-in-Memory on SoC for AIoT Applications. | Kangyi Qiu, Yaojun Zhang, Bonan Yan, Ru Huang |
| 2022 | DAC | ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses. | Ziru Li, Qilin Zheng, Bonan Yan, Ru Huang, Bing Li, Yiran Chen |
| 2022 | DAC | AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS. | Zuodong Zhang, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang |
| 2022 | DATE | EventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis. | Zuodong Zhang, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang |
| 2022 | HPCA | Enabling High-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network. | Xingchen Li, Bingzhe Wu, Guangyu Sun, Zhe Zhang, Zhihang Yuan, Runsheng Wang, Ru Huang, Dimin Niu, Hongzhong Zheng, Zhichao Lu, Liang Zhao, Meng-Fan Marvin Chang, Tianchan Guan, Xin Si |
| 2022 | ICCAD | DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks. | Yikan Qiu, Yufei Ma, Wentao Zhao, Meng Wu, Le Ye, Ru Huang |
| 2022 | ICCAD | DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography. | Qipan Wang, Xiaohan Gao, Yibo Lin, Runsheng Wang, Ru Huang |
| 2021 | FPGA | SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA. | Yufei Ma, Gokul Krishnan, Yu Cao, Le Ye, Ru Huang |
| 2021 | ICCAD | DALTA: A Decomposition-based Approximate Lookup Table Architecture. | Chang Meng, Zhiyuan Xiang, Niyiqiu Liu, Yixuan Hu, Jiahao Song, Runsheng Wang, Ru Huang, Weikang Qian |
| 2021 | ISCAS | A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations. | Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang |
| 2021 | ISCAS | Approximate Logic Synthesis in the Loop for Designing Low-Power Neural Network Accelerator. | Yifan Qian, Chang Meng, Yawen Zhang, Weikang Qian, Runsheng Wang, Ru Huang |
| 2021 | ISCAS | A High Accuracy Multiple-Command Speech Recognition ASIC Based on Configurable One-Dimension Convolutional Neural Network. | Lindong Wu, Zongwei Wang, Ming Zhao, Wei Hu, Yimao Cai, Ru Huang |
| 2021 | ISCAS | A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS. | Yi Zhong, Xiaoxin Cui, Yisong Kuang, Kefei Liu, Yuan Wang, Ru Huang |
| 2020 | DAC | Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks. | Qilin Zheng, Zongwei Wang, Zishun Feng, Bonan Yan, Yimao Cai, Ru Huang, Yiran Chen, Chia-Lin Yang, Hai Helen Li |
| 2020 | DATE | When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic Computing. | Yawen Zhang, Sheng Lin, Runsheng Wang, Yanzhi Wang, Yuan Wang, Weikang Qian, Ru Huang |
| 2020 | ICCAD | MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory Block. | Qilin Zheng, Xingchen Li, Zongwei Wang, Guangyu Sun, Yimao Cai, Ru Huang, Yiran Chen, Hai Li |
| 2020 | ISCAS | A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC with 86.7% Peak Efficiency using Frequency-Programmable Oscillator and Hybrid Zero Current Detection. | Xiaolong Chen, Enbin Gong, Hao Zhang, Le Ye, Ru Huang |
| 2020 | ISCAS | 2.4-GHz 16-QAM Passive Backscatter Transmitter for Wireless Self-Power Chips in IoT. | Enbin Gong, Hao Zhang, Xiaolong Chen, Le Ye, Ru Huang |
| 2020 | ISCAS | Accurate and Energy-Efficient Implementation of Non-Linear Adder in Parallel Stochastic Computing using Sorting Network. | Yawen Zhang, Runsheng Wang, Yixuan Hu, Weikang Qian, Yanzhi Wang, Yuan Wang, Ru Huang |
| 2019 | ISCAS | Ultra-Low Power Hybrid TFET-MOSFET Topologies for Standard Logic Cells with Improved Comprehensive Performance. | Zhixuan Wang, Yuan Zhong, Cheng Chen, Le Ye, Qianqian Huang, Libo Yang, Yangyuan Wang, Ru Huang |
| 2019 | ISCAS | Enhance the Robustness to Time Dependent Variability of ReRAM-Based Neuromorphic Computing Systems with Regularization and 2R Synapse. | Qilin Zheng, Jian Kang, Zongwei Wang, Yimao Cai, Ru Huang, Bing Li, Yiran Chen, Hai Helen Li |
| 2018 | ASPDAC | Layout-dependent aging mitigation for critical path timing. | Che-Lun Hsu, Shaofeng Guo, Yibo Lin, Xiaoqing Xu, Meng Li, Runsheng Wang, Ru Huang, David Z. Pan |
| 2018 | ISCAS | Evaluation of SRAM V | Shaofeng Guo, Zhenghan Lin, Runsheng Wang, Dongyuan Mao, Yangyuan Wang, Ru Huang |
| 2018 | ISCAS | Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. | Guangyi Lu, Yuan Wang, Lizhong Zhang, Yize Wang, Ru Huang, Xing Zhang |
| 2018 | ISCAS | Combinational Access Tunnel FET SRAM for Ultra-Low Power Applications. | Libo Yang, Jiadi Zhu, Cheng Chen, Zhixuan Wang, Zexue Liu, Qianqian Huang, Le Ye, Ru Huang |
| 2018 | ISCAS | A Multi-Mode Silicon Neuron Circuit With High Robustness Against PVT Variation. | Lu Zhang, Jin Zhang, Yuan Wang, Xing Zhang, Ru Huang |
| 2017 | ICCAD | Towards reliability-aware circuit design in nanoscale FinFET technology: - New-generation aging model and circuit reliability simulator. | Shaofeng Guo, Runsheng Wang, Zhuoqing Yu, Peng Hao, Pengpeng Ren, Yangyuan Wang, Siyu Liao, Chunyi Huang, Tianlei Guo, Alvin Chen, Jushan Xie, Ru Huang |
| 2017 | ISCAS | Benchmarking TFET from a circuit level perspective: Applications and guideline. | Lingyi Guo, Le Ye, Cheng Chen, Qianqian Huang, Libo Yang, Zhu Lv, Xia An, Ru Huang |
| 2017 | ISCAS | Compact digital-controlled neuromorphic circuit with low power consumption. | Jin Zhang, Yuan Wang, Xing Zhang, Ru Huang |
| 2014 | ISCAS | Resistive switching in organic memory devices for flexible applications. | Ru Huang, Yimao Cai, Yefan Liu, Wenliang Bai, Yongbian Kuang, Yangyuan Wang |
| 2013 | ISCAS | SAW-less GNSS front-end amplifier with 80.4-dB GSM blocker suppression using CMOS directional coupler notch filter. | Yongan Zheng, Le Ye, Long Chen, Huailin Liao, Ru Huang |
| 2013 | ISLPED | Heterogeneous integration of nano enabling devices for 3D ICs. | Li Wang, Rui Ma, Chen Zhang, Zongyu Dong, Xin Wang, Zitao Shi, Jian Liu, Lin Lin, Hui Zhao, Fei Lu, Qiang Fang, Chen Yang, Jing Zhan, Tianling Ren, Xinxin Li, Ru Huang, Albert Wang |
| 2012 | ISCAS | A +21.2 dBm out-of-band IIP3 0.2-3GHz RF front-end using impedance translation technique. | Long Chen, Chuan Wang, Chen Li, Le Ye, Huailin Liao, Ru Huang |
| 2012 | ISCAS | Cost-efficient CMOS RF tunable bandpass filter with active inductor-less biquads. | Yixiao Wang, Le Ye, Huailin Liao, Ru Huang |
| 2012 | ISCAS | Widely reconfigurable 8 | Le Ye, Yixiao Wang, Long Chen, Huailin Liao, Ru Huang |
| 2011 | ISCAS | A 0.47mW 6 | Le Ye, Congyin Shi, Huailin Liao, Ru Huang |
| 2010 | ICMLC | The design of energy-saving filtering mechanism for sensor networks. | Ru Huang, Guang-Hui Xu |