| 2026 | ASPDAC | LAPA: Log-Domain Prediction-Driven Dynamic Sparsity Accelerator for Transformer Model. | Huizheng Wang, Hongbin Wang, Shaojun Wei, Yang Hu, Shouyi Yin |
| 2026 | ASPDAC | BitStopper: An Efficient Transformer Attention Accelerator via Stage-fusion and Early Termination. | Huizheng Wang, Hongbin Wang, Shaojun Wei, Yang Hu, Shouyi Yin |
| 2026 | ASPDAC | MoBiLE: Efficient Mixture-of-Experts Inference on Consumer GPU with Mixture of Big Little Experts. | Yushu Zhao, Yubin Qin, Yang Wang, Xiaolong Yang, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin |
| 2026 | ASPLOS | XY-Serve: End-to-End Versatile Production Serving for Dynamic LLM Workloads. | Mingcong Song, Xinru Tang, Fengfan Hou, Jing Li, Wei Wei, Yipeng Ma, Runqiu Xiao, Hongjie Si, Dingcheng Jiang, Shouyi Yin, Yang Hu, Guoping Long |
| 2026 | DATE | Hetero-ChipletSim: Bridging Chiplet, Interconnect and Packaging Heterogeneity in Multi-Chiplet System Simulation. | Xuguang Yuan, Jiangyuan Gu, Qidie Wu, Yang Hu, Shaojun Wei, Shouyi Yin |
| 2026 | HPCA | HR-DCIM: High-Reliability Floating-Point Digital CIM Architecture With Unified Low-Cost Iterative Error Correction. | Zhen He, Yiqi Wang, Zhiheng Yue, Zihan Wu, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin |
| 2026 | HPCA | ReThermal: Co-Design of Thermal-Aware Static and Dynamic Scheduling for LLM Training on Liquid-Cooled Wafer-Scale Chips. | Chengran Li, Huizheng Wang, Jiaxin Liu, Jingyao Liu, Zhiheng Yue, Xia Li, Shenfei Jiang, Jinyi Deng, Yang Hu, Shouyi Yin |
| 2026 | HPCA | MoEntwine: Unleashing the Potential of Wafer-Scale Chips for Large-Scale Expert Parallel Inference. | Xinru Tang, Jingxiang Hou, Dingcheng Jiang, Taiquan Wei, Jiaxin Liu, Jinyi Deng, Huizheng Wang, Qize Yang, Haoran Shang, Chao Li, Yang Hu, Shouyi Yin |
| 2026 | HPCA | WATOS: Efficient LLM Training Strategies and Architecture Co-Exploration for Wafer-Scale Chip. | Huizheng Wang, Zichuan Wang, Hongbin Wang, Jingxiang Hou, Taiquan Wei, Chao Li, Yang Hu, Shouyi Yin |
| 2026 | HPCA | TEMP: A Memory Efficient Physical-Aware Tensor Partition-Mapping Framework on Wafer-Scale Chips. | Huizheng Wang, Taiquan Wei, Zichuan Wang, Dingcheng Jiang, Qize Yang, Jiaxin Liu, Jingxiang Hou, Chao Li, Jinyi Deng, Yang Hu, Shouyi Yin |
| 2026 | HPCA | PADE: A Predictor-Free Sparse Attention Accelerator via Unified Execution and Stage Fusion. | Huizheng Wang, Hongbin Wang, Zichuan Wang, Zhiheng Yue, Yang Wang, Chao Li, Yang Hu, Shouyi Yin |
| 2026 | HPCA | FACE: Fully Overlapped PD Scheduling and Multi-Level Architecture Co-Exploration on Wafer. | Zheng Xu, Dehao Kong, Jiaxin Liu, Dingcheng Jiang, Xu Dai, Jinyi Deng, Yang Hu, Shouyi Yin |
| 2025 | ASPDAC | DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures. | Haojia Hui, Jiangyuan Gu, Xunbo Hu, Shaojun Wei, Shouyi Yin |
| 2025 | DAC | GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs. | Mingyang Kou, Weiqing Ji, Shouyi Yin, Hailong Yao |
| 2025 | HPCA | ER-DCIM: Error-Resilient Digital CIM Architecture with Run-Time MAC-Cell Error Correction. | Zhen He, Yiqi Wang, Zihan Wu, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin |
| 2025 | ICCAD | P2P-Chiplet: Partition and Placement Co-Optimization for Multi-Chiplet Architecture. | Qidie Wu, Jiangyuan Gu, Xuguang Yuan, Shaojun Wei, Shouyi Yin |
| 2025 | ICCD | RAM-Wafer: RL-Based Automatic Mapping Framework for Large-Scale AI Training on Wafer-Scale Computing. | Xu Dai, Dehao Kong, Xufeng He, Zijun Xu, Shaopeng Zhai, Yang Hu, Shouyi Yin |
| 2025 | ISCA | WSC-LLM: Efficient LLM Service and Architecture Co-exploration for Wafer-scale Chips. | Zheng Xu, Dehao Kong, Jiaxin Liu, Jinxi Li, Jingxiang Hou, Xu Dai, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin |
| 2025 | ISCA | PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer. | Qize Yang, Taiquan Wei, Sihan Guan, Chengran Li, Haoran Shang, Jinyi Deng, Huizheng Wang, Chao Li, Lei Wang, Yan Zhang, Shouyi Yin, Yang Hu |
| 2025 | ISCA | Cramming a Data Center into One Cabinet, a Co-Exploration of Computing and Hardware Architecture of Waferscale Chip. | Xingmao Yu, Dingcheng Jiang, Jinyi Deng, Jingyao Liu, Chao Li, Shouyi Yin, Yang Hu |
| 2025 | ISCAS | STPE: An Energy-Efficient Edge-Device Transformer Inference Processor with Multi-Mode Data-Compression Scheme. | Zhou Wang, Haochen Du, Vivek Mohan, Jiuren Zhou, Zhou Shu, Yanqing Xu, Baoyi Han, Xiaonan Tang, Shushan Qiao, Shouyi Yin, Anil A. Bharath, Emmanuel M. Drakakis |
| 2025 | ISCAS | GPE: A High-Performance Edge GNN Inference Processor with Multi-Parallelism Format-Variation Mechanism. | Zhou Wang, Haochen Du, Jiuren Zhou, Zhou Shu, Yanqing Xu, Vivek Mohan, Baoyi Han, Xiaonan Tang, Shushan Qiao, Shouyi Yin, Anil A. Bharath, Emmanuel M. Drakakis |
| 2025 | MICRO | MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness. | Huizheng Wang, Zichuan Wang, Zhiheng Yue, Yousheng Long, Taiquan Wei, Jianxun Yang, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin |
| 2025 | MICRO | 3D-PATH: A Hierarchy LUT Processing-in-memory Accelerator with Thermal-aware Hybrid Bonding Integration. | Zhiheng Yue, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin |
| 2024 | DAC | PMP: Pattern Morphing-based Memory Partitioning in High-Level Synthesis. | Dajiang Liu, Decai Pan, Xiao Xiong, Jiaxing Shang, Shouyi Yin |
| 2024 | DAC | Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. | Xujiang Xiang, Zhiheng Yue, Yuxuan Li, Liuxin Lv, Shaojun Wei, Yang Hu, Shouyi Yin |
| 2024 | DAC | GSPO: A Graph Substitution and Parallelization Joint Optimization Framework for DNN Inference. | Zheng Xu, Xu Dai, Shaojun Wei, Shouyi Yin, Yang Hu |
| 2024 | DAC | FQP: A Fibonacci Quantization Processor with Multiplication-Free Computing and Topological-Order Routing. | Xiaolong Yang, Yang Wang, Yubin Qin, Jiachen Wang, Shaojun Wei, Yang Hu, Shouyi Yin |
| 2024 | DAC | CAP: A General Purpose Computation-in-memory with Content Addressable Processing Paradigm. | Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin |
| 2024 | HPCA | E2EMap: End-to-End Reinforcement Learning for CGRA Compilation via Reverse Mapping. | Dajiang Liu, Yuxin Xia, Jiaxing Shang, Jiang Zhong, Peng Ouyang, Shouyi Yin |
| 2024 | ISCA | MECLA: Memory-Compute-Efficient LLM Accelerator with Scaling Sub-matrix Partition. | Yubin Qin, Yang Wang, Zhiren Zhao, Xiaolong Yang, Yang Zhou, Shaojun Wei, Yang Hu, Shouyi Yin |
| 2024 | ISCA | Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture. | Zhiheng Yue, Huizheng Wang, Jiahao Fang, Jinyi Deng, Guangyang Lu, Fengbin Tu, Ruiqi Guo, Yuxuan Li, Yubin Qin, Yang Wang, Chao Li, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin |
| 2024 | MICRO | SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling. | Huizheng Wang, Jiahao Fang, Xinru Tang, Zhiheng Yue, Jinxi Li, Yubin Qin, Sihan Guan, Qinze Yang, Yang Wang, Chao Li, Yang Hu, Shouyi Yin |
| 2023 | DAC | DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs. | Dajiang Liu, Di Mou, Rong Zhu, Yan Zhuang, Jiaxing Shang, Jiang Zhong, Shouyi Yin |
| 2023 | DAC | CPE: An Energy-Efficient Edge-Device Training with Multi-dimensional Compression Mechanism. | Zhou Wang, Jingchuan Wei, Boxiao Han, Hongjun He, Leibo Liu, Shaojun Wei, Shouyi Yin |
| 2023 | DAC | RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA. | Qidie Wu, Jiangyuan Gu, Youxu Lin, Boxiao Han, Hongjun He, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin |
| 2023 | ISCA | FACT: FFN-Attention Co-optimized Transformer Architecture with Eager Correlation Prediction. | Yubin Qin, Yang Wang, Dazheng Deng, Zhiren Zhao, Xiaolong Yang, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin |
| 2023 | MICRO | Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane. | Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li, Linyun Zhang, Boxiao Han, Hongjun He, Fengbin Tu, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin |
| 2022 | DAC | Efficient access scheme for multi-bank based NTT architecture through conflict graph. | Xiangren Chen, Bohan Yang, Yong Lu, Shouyi Yin, Shaojun Wei, Leibo Liu |
| 2022 | DAC | Mixed-granularity parallel coarse-grained reconfigurable architecture. | Jinyi Deng, Linyun Zhang, Lei Wang, Jiawei Liu, Kexiang Deng, Shibin Tang, Jiangyuan Gu, Boxiao Han, Fei Xu, Leibo Liu, Shaojun Wei, Shouyi Yin |
| 2022 | DAC | MC-CIM: a reconfigurable computation-in-memory for efficient stereo matching cost computation. | Zhiheng Yue, Yabing Wang, Leibo Liu, Shaojun Wei, Shouyi Yin |
| 2022 | HPCA | Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems. | Yibo Wu, Liang Wang, Xiaohang Wang, Jie Han, Jianfeng Zhu, Honglan Jiang, Shouyi Yin, Shaojun Wei, Leibo Liu |
| 2022 | HPCA | Atomic Dataflow based Graph-Level Workload Orchestration for Scalable DNN Accelerators. | Shixuan Zheng, Xianjue Zhang, Leibo Liu, Shaojun Wei, Shouyi Yin |
| 2022 | ISCA | CaSMap: agile mapper for reconfigurable spatial architectures by automatically clustering intermediate representations and scattering mapping process. | Xingchen Man, Jianfeng Zhu, Guihuan Song, Shouyi Yin, Shaojun Wei, Leibo Liu |
| 2021 | ASPDAC | Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs. | Cheng Li, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2021 | ASPDAC | A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating. | Song Zhang, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2021 | ASRU | GLMSnet: Single Channel Speech Separation Framework in Noisy and Reverberant Environments. | Huiyu Shi, Xi Chen, Tianlong Kong, Shouyi Yin, Peng Ouyang |
| 2021 | DAC | ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving In DNN Training. | Xinhan Lin, Liang Sun, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei, Shouyi Yin |
| 2021 | DATE | HeteroKV: A Scalable Line-rate Key-Value Store on Heterogeneous CPU-FPGA Platforms. | Haichang Yang, Zhaoshi Li, Jiawei Wang, Shouyi Yin, Shaojun Wei, Leibo Liu |
| 2021 | HPCA | FuseKNA: Fused Kernel Convolution based Accelerator for Deep Neural Networks. | Jianxun Yang, Zhao Zhang, Zhuangzhi Liu, Jing Zhou, Leibo Liu, Shaojun Wei, Shouyi Yin |
| 2021 | ICCAD | Polyhedral-based Pipelining of Imperfectly-Nested Loop for CGRAs. | Dajiang Liu, Ting Liu, Xingyu Mo, Jiaxing Shang, Shouyi Yin |
| 2021 | Interspeech | Dynamic Multi-Scale Convolution for Dialect Identification. | Tianlong Kong, Shouyi Yin, Dawei Zhang, Wang Geng, Xin Wang, Dandan Song, Jinwen Huang, Huiyu Shi, Xiaorui Wang |
| 2021 | ISCA | ABC-DIMM: Alleviating the Bottleneck of Communication in DIMM-based Near-Memory Processing with Inter-DIMM Broadcast. | Weiyi Sun, Zhaoshi Li, Shouyi Yin, Shaojun Wei, Leibo Liu |
| 2020 | DAC | TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. | Mingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin |
| 2020 | DAC | STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction. | Feng Xiong, Fengbin Tu, Man Shi, Yang Wang, Leibo Liu, Shaojun Wei, Shouyi Yin |
| 2020 | FCCM | A High-performance Inference Accelerator Exploiting Patterned Sparsity in CNNs. | Ning Li, Leibo Liu, Shaojun Wei, Shouyi Yin |
| 2020 | ICASSP | PAGAN: A Phase-Adapted Generative Adversarial Networks for Speech Enhancement. | Peishuo Li, Zihang Jiang, Shouyi Yin, Dandan Song, Peng Ouyang, Leibo Liu, Shaojun Wei |
| 2020 | Interspeech | Transformer with Bidirectional Decoder for Speech Recognition. | Xi Chen, Songyang Zhang, Dandan Song, Peng Ouyang, Shouyi Yin |
| 2020 | Interspeech | THUEE System for NIST SRE19 CTS Challenge. | Ruyun Li, Tianyu Liang, Dandan Song, Yi Liu, Yangcheng Wu, Can Xu, Peng Ouyang, Xianwei Zhang, Xianhong Chen, Weiqiang Zhang, Shouyi Yin, Liang He |
| 2020 | ISCA | GraphABCD: Scaling Out Graph Analytics with Asynchronous Block Coordinate Descent. | Yifan Yang, Zhaoshi Li, Yangdong Deng, Zhiwei Liu, Shouyi Yin, Shaojun Wei, Leibo Liu |
| 2020 | MICRO | CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture. | Dibei Chen, Zhaoshi Li, Tianzhu Xiong, Zhiwei Liu, Jun Yang, Shouyi Yin, Shaojun Wei, Leibo Liu |
| 2020 | MICRO | TFE: Energy-efficient Transferred Filter-based Engine to Compress and Accelerate Convolutional Neural Networks. | Huiyu Mo, Leibo Liu, Wenjing Hu, Wenping Zhu, Qiang Li, Ang Li, Shouyi Yin, Jian Chen, Xiaowei Jiang, Shaojun Wei |
| 2019 | ASRU | Small-Footprint Keyword Spotting with Graph Convolutional Network. | Xi Chen, Shouyi Yin, Dandan Song, Peng Ouyang, Leibo Liu, Shaojun Wei |
| 2019 | FPGA | Constructing Concurrent Data Structures on FPGA with Channels. | Hui Yan, Zhaoshi Li, Leibo Liu, Shouyi Yin, Shaojun Wei |
| 2019 | ICCAD | ReDESK: A Reconfigurable Dataflow Engine for Sparse Kernels on Heterogeneous Platforms. | Kai Lu, Zhaoshi Li, Leibo Liu, Jiawei Wang, Shouyi Yin, Shaojun Wei |
| 2019 | ISCAS | A Reliable Physical Unclonable Function Based on Differential Charging Capacitors. | Hang Yuan, Wei Guo, Chip-Hong Chang, Yuan Cao, Shaojun Wei, Shouyi Yin, Chenchen Deng, Leibo Liu, Wei Ge, Fan Zhang |
| 2019 | MICRO | FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory. | Zhaoshi Li, Leibo Liu, Yangdong Deng, Jiawei Wang, Zhiwei Liu, Shouyi Yin, Shaojun Wei |
| 2018 | DAC | LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA. | Xinhan Lin, Shouyi Yin, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei |
| 2018 | DAC | An efficient kernel transformation architecture for binary- and ternary-weight neural network inference. | Shixuan Zheng, Yonggang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2018 | ISCA | RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM. | Fengbin Tu, Weiwei Wu, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2018 | ISCAS | Bit-width Adaptive Accelerator Design for Convolution Neural Network. | Jianxin Guo, Shouyi Yin, Peng Ouyang, Fengbin Tu, Shibin Tang, Leibo Liu, Shaojun Wei |
| 2018 | ISCAS | An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing. | Zhihui Wang, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei |
| 2017 | ASPDAC | Energy-aware loops mapping on multi-vdd CGRAs without performance degradation. | Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2017 | DAC | Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect. | Jiangyuan Gu, Shouyi Yin, Shaojun Wei |
| 2017 | DAC | A Fast and Power Efficient Architecture to Parallelize LSTM based RNN for Cognitive Intelligence Applications. | Peng Ouyang, Shouyi Yin, Shaojun Wei |
| 2017 | DAC | Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM. | Shouyi Yin, Zhicong Xie, Shaojun Wei |
| 2017 | FCCM | Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA. | Jianxin Guo, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei |
| 2017 | FPGA | Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). | Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei |
| 2017 | FPGA | Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only). | Shouyi Yin, Dajiang Liu, Lifeng Sun, Xinhan Lin, Leibo Liu, Shaojun Wei |
| 2017 | ISCA | Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware. | Zhaoshi Li, Leibo Liu, Yangdong Deng, Shouyi Yin, Yao Wang, Shaojun Wei |
| 2017 | ISCAS | Memory fartitioning-based modulo scheduling for high-level synthesis. | Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei |
| 2017 | ISCAS | DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach. | Shouyi Yin, Dajiang Liu, Lifeng Sun, Leibo Liu, Shaojun Wei |
| 2017 | SAC | Multi-CNN and decision tree based driving behavior evaluation. | Shouyi Yin, Jinjin Duan, Peng Ouyang, Leibo Liu, Shaojun Wei |
| 2016 | ASPDAC | Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures. | Xinhan Lin, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2016 | DAC | Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays. | Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei |
| 2016 | ICCAD | Multibank memory optimization for parallel data access in multiple data arrays. | Shouyi Yin, Zhicong Xie, Chenyue Meng, Leibo Liu, Shaojun Wei |
| 2016 | ICCAD | Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory. | Shouyi Yin, Xianqing Yao, Tianyi Lu, Leibo Liu, Shaojun Wei |
| 2015 | ASPDAC | A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures. | Leibo Liu, Yu Ren, Chenchen Deng, Shouyi Yin, Shaojun Wei, Jie Han |
| 2015 | ASPDAC | Battery-aware mapping optimization of loop nests for CGRAs. | Yu Peng, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2015 | DAC | A 127 fps in full hd accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extraction. | Guangli Jiang, Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei |
| 2015 | DAC | Efficient memory partitioning for parallel data access in multidimensional arrays. | Chenyue Meng, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei |
| 2015 | DAC | Acceleration of control flows on reconfigurable architecture with a composite method. | Junbin Wang, Leibo Liu, Jianfeng Zhu, Shouyi Yin, Shaojun Wei |
| 2015 | DATE | RNA: a reconfigurable architecture for hardware neural acceleration. | Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei |
| 2015 | DATE | Joint affine transformation and loop pipelining for mapping nested loop on CGRAs. | Shouyi Yin, Dajiang Liu, Leibo Liu, Shaojun Wei, Yike Guo |
| 2015 | DATE | Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache. | Shouyi Yin, Jiakun Li, Leibo Liu, Shaojun Wei, Yike Guo |
| 2015 | FPGA | A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only). | Leibo Liu, Yingjie Victor Chen, Dong Wang, Min Zhu, Shouyi Yin, Shaojun Wei |
| 2015 | FPGA | A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only). | Junbin Wang, Leibo Liu, Jianfeng Zhu, Shouyi Yin, Shaojun Wei |
| 2015 | FPGA | Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only). | Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei |
| 2015 | ICCAD | Acceleration of Nested Conditionals on CGRAs via Trigger Scheme. | Shouyi Yin, Pengcheng Zhou, Leibo Liu, Shaojun Wei |
| 2015 | ISCAS | Neural approximating architecture targeting multiple application domains. | Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei |
| 2015 | WACV | A Multi-modal 2D + 3D Face Recognition Method with a Novel Local Feature Descriptor. | Xu Dai, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei |
| 2014 | DATE | Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms. | Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei |
| 2014 | FCCM | Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures. | Dajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2014 | FIE | Teach Reconfigurable Computing using mixed-grained fabrics based hardware infrastructure. | Chenchen Deng, Leibo Liu, Zhaoshi Li, Shouyi Yin, Shaojun Wei |
| 2014 | FPL | Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor. | Chen Yang, Leibo Liu, Yansheng Wang, Shouyi Yin, Peng Cao, Shaojun Wei |
| 2014 | ICPR | A FAST Extreme Illumination Robust Feature in Affine Space. | Peng Ouyang, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2014 | ISCAS | Map-reduce inspired loop parallelization on CGRA. | Shengjia Shao, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2014 | ISCAS | A parallel hardware architecture for fast integral image computing. | Yuchi Zhang, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei |
| 2014 | ISCAS | A 65 nm uneven-dual-core SoC based platform for multi-device collaborative computing. | Wenping Zhu, Leibo Liu, Shouyi Yin, Yuan Dong, Shaojun Wei, Eugene Y. Tang, Jiqiang Song, Jinzhan Peng |
| 2013 | DAC | Polyhedral model based mapping optimization of loop nests for CGRAs. | Dajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2013 | ISCAS | Implementation of multi-standard video decoding algorithms on a coarse-grained reconfigurable multimedia processor. | Leibo Liu, Yingjie Victor Chen, Shouyi Yin, Dong Wang, Xing Wang, Shaojun Wei, Li Zhou, Hao Lei, Peng Cao |
| 2013 | ISCAS | Affine transformations for communication and reconfiguration optimization of loops on CGRAs. | Dajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2013 | ISCAS | A VLSI architecture for enhancing the fault tolerance of NoC using quad-spare mesh topology and dynamic reconfiguration. | Yu Ren, Leibo Liu, Shouyi Yin, Qinghua Wu, Shaojun Wei, Jie Han |
| 2013 | ISCAS | An inductive-coupling interconnected application-specific 3D NoC design. | Zhen Zhang, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2012 | ISCAS | Reducing configuration contexts for coarse-grained reconfigurable architecture. | Shouyi Yin, Chongyong Yin, Leibo Liu, Min Zhu, Yansheng Wang, Shaojun Wei |
| 2010 | ISCAS | Parallel implementation of computing-intensive decoding algorithms of H.264 on reconfigurable SoC. | Tongsheng Geng, Leibo Liu, Shouyi Yin, Min Zhu, Wen Jia, Shaojun Wei |
| 2010 | ISCAS | A VLSI design of sensor node for wireless image sensor network. | Renyan Zhou, Leibo Liu, Shouyi Yin, Ao Luo, Xinkai Chen, Shaojun Wei |
| 2010 | ISCAS | A reconfigurable multi-processor SoC for media applications. | Min Zhu, Leibo Liu, Shouyi Yin, Yansheng Wang, Wenjie Wang, Shaojun Wei |
| 2006 | Qshine | Prediction-based routing for real time communications in wireless multi-hop networks. | Shouyi Yin, Yongqiang Xiong, Qian Zhang, Xiaokang Lin |
| 2005 | WCNC | Adaptive load balancing in mobile ad hoc networks. | Shouyi Yin, Xiaokang Lin |