Skip to content

Srivaths Ravi

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

65

Venues

11

Active years

1998–2022

Best venue rank

A*

Where they publish

Papers

65 indexed papers, newest first.

YearVenueTitleAuthors
2022ETSGraph Theory Approach for Multi-site ATE Board Parameter Extraction.Abraham Steenhoek, Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2022ITCOptimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing.Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2022VTSThe Least-Squares Approach to Systematic Error Identification and Calibration in Semiconductor Multisite Testing.Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2021ETSAn Ordinal Optimization-Based Approach To Die Distribution Estimation For Massive Multi-site Testing Validation: A Case Study.Isaac Bruce, Praise O. Farayola, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2021ITCSystematic Hardware Error Identification and Calibration for Massive Multisite Testing.Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2020VTSQuantile - Quantile Fitting Approach to Detect Site to Site Variations in Massive Multi-site Testing.Praise O. Farayola, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2017ITCDemystifying automotive safety and security for semiconductor developer.V. Prasanth, David Foley, Srivaths Ravi
2017VTSForeword.Yiorgos Makris, Srivaths Ravi, Amit Majumdar
2015VLSIDTutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems.Prabhat Mishra, Swarup Bhunia, Srivaths Ravi
2014ITCAt-speed capture power reduction using layout-aware granular clock gate enable controls.Raashid Shaikh, Pradeep Wilson, Khushboo Agarwal, H. V. Sanjay, Rajesh Tiwari, Kaushik Lath, Srivaths Ravi
2014VLSIDTutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices.Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula
2011VLSIDMulti-CoDec Configurations for Low Power and High Quality Scan Test.Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi
2010ITCMethodology for early and accurate test power estimation at RTL.Abhay Singh, Milan Shetty, Srivaths Ravi, Ravindra Nibandhe
2010VTSA generic low power scan chain wrapper for designs using scan compression.Amit Sabne, Rajesh Tiwari, Abhijeet Shrivastava, Srivaths Ravi, Rubin A. Parekhji
2008VLSIDVariability-Tolerant Register-Transfer Level Synthesis.Anish Muttreja, Srivaths Ravi, Niraj K. Jha
2008VTSA Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips.Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi, Rubin A. Parekhji
2007DATEEnergy and execution time analysis of a software-based trusted platform module.Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2007ICCADMethodology for low power test pattern generation using activity threshold control logic.Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji
2007ITCPower-aware test: Challenges and solutions.Srivaths Ravi
2007VLSIDTutorial T1: Designing Secure SoCs.Srivaths Ravi, Stefan Mangard
2006DACSoftware architecture exploration for high-performance security processing on a multiprocessor mobile SoC.Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
2006DACSystematic software-based self-test for pipelined processors.Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi
2006DATEArchitectures for efficient face authentication in embedded systems.Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006DATESatisfiability-based framework for enabling side-channel attacks on cryptographic software.Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
2006ISCCActive Learning Driven Data Acquisition for Sensor Networks.Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2006VLSIDImpact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors.Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
2006VLSIDHybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005CASESSECA: security-enhanced communication architecture.Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
2005DACPower emulation: a new paradigm for power estimation.Joel Coburn, Srivaths Ravi, Anand Raghunathan
2005DACEfficient fingerprint-based user authentication for embedded systems.Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005DACHybrid simulation for embedded software energy estimation.Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2005DATESecure Embedded Processing through Hardware-Assisted Run-Time Monitoring.Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005DATEHardware Accelerated Power Estimation.Joel Coburn, Srivaths Ravi, Anand Raghunathan
2005VLSIDHeterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip.Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
2005VLSIDSynthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004DACAutomated energy/performance macromodeling of embedded software.Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2004DACSecurity as a new dimension in embedded system design.Srivaths Ravi, Paul C. Kocher, Ruby B. Lee, Gary McGraw, Anand Raghunathan
2004ICCADHigh-level synthesis using computation-unit integrated memories.Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004ICCADPower estimation for cycle-accurate functional descriptions of hardware.Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004VLSIDEnergy-Optimizing Source Code Transformations for OS-driven Embedded Software.Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004VLSIDTamper Resistance Mechanisms for Secure, Embedded Systems.Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
2003DACA scalable software-based self-test methodology for programmable processors.Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey
2003DATETransport Protocol Optimization for Energy Efficient Wireless Embedded Systems.Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi
2003DATEEnergy Estimation for Extensible Processors.Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003DATESecuring Mobile Appliances: New Challenges for the System Designer.Anand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater
2003ICCADSynthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications.Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003ICCADA Scalable Application-Specific Processor Synthesis Methodology.Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003ICCDTest Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach.Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha
2003ISLPEDAnalyzing the energy consumption of security protocols.Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003VLSIDEmbedding Security in Wireless Embedded Systems.Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
2003VLSIDEfficient RTL Power Estimation for Large Designs.Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
2002DACSystem design methodologies for a wireless security processing platform.Srivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, Murugan Sankaradass
2002ICCADHigh-level synthesis of distributed logic-memory architectures.Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2002ICCADSynthesis of custom processors based on extensible platforms.Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2001ICCADTransient Power Management Through High Level Synthesis.Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
2001ITCFast test generation for circuits with RTL and gate-level views.Srivaths Ravi, Niraj K. Jha
2001VLSIDSynthesis of System-on-a-chip for Testability.Srivaths Ravi, Niraj K. Jha
2000ICCDA Technique for Identifying RTL and Gate-Level Correspondences.Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana
2000ITC: Reducing test application time in high-level test generation.Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
2000VLSIDHigh-Level Synthesis with Variable-Latency Components.Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana
1999ICCADA framework for testing core-based systems-on-a-chip.Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1999VTSTAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST.Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1998ICCADRemoval of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions.Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1998ITCTAO: regular expression based high-level testability analysis and optimization.Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1998VLSIDController Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits.Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey