| 2009 | IJCNN | Obstacle to training SpikeProp networks - Cause of surges in training process -. | Haruhiko Takase, Masaru Fujita, Hiroharu Kawanaka, Shinji Tsuruoka, Hidehiko Kita, Terumine Hayashi |
| 2008 | IJCNN | Shape of error surfaces in SpikeProp. | Masaru Fujita, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi |
| 2007 | ICCE | Descriptive Answer Clustering System for Immediate Feedback. | Kazutaka Noro, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi, Naoki Morita |
| 2007 | IJCNN | Enhancing both generalization and fault tolerance of multilayer neural networks. | Haruhiko Takase, Masahiko Masahiko, Hidehiko Kita, Terumine Hayashi |
| 2006 | IJCNN | Fault tolerant training algorithm for multi-layer neural networks focused on hidden unit activities. | Haruhiko Takase, Hidehiko Kita, Terumine Hayashi |
| 2005 | IJCNN | Dynamic construction of fault tolerant multi-layer neural networks. | Haruhiko Takase, Ayumi Nobuto, Hidehiko Kita, Terumine Hayashi |
| 2004 | ASPDAC | Test data compression technique using selective don't-care identification. | Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase |
| 2004 | IJCNN | A study on the simple penalty term to the error function from the viewpoint of fault tolerant training. | Haruhiko Takase, Hidehiko Kita, Terumine Hayashi |
| 2000 | IJCNN | Evaluation Function for Fault Tolerant Multi-Layer Neural Networks. | Haruhiko Takase, Tsuyoshi Shinogi, Terumine Hayashi, Hidehiko Kita |
| 1999 | ASPDAC | A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition. | Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi |
| 1998 | VTS | A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Fault. | Tsuyoshi Shinogi, Terumine Hayashi |
| 1997 | ASPDAC | An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits. | Kai Zhang, Haruhiko Takase, Terumine Hayashi, Hidehiko Kita |
| 1992 | ITC | Sequential Test Generation Based on Real-Value Logic. | Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi |
| 1991 | ICCAD | Timing-Oriented Routers for PCB Layout Design of High-Performance Computers. | Yutaka Sekiyama, Yasuyuki Fujihara, Terumine Hayashi, Mitsuho Seki, Jiro Kusuhara, Kazuhiko Iijima, Masahiro Takakura, Koji Fukatani |
| 1990 | IJCNN | LSI module placement methods using neural computation networks. | Hiroshi Date, Mitsuho Seki, Terumine Hayashi |
| 1989 | ITC | Enhanced Delay Test Generator for High-Speed Logic LSIs. | Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama |
| 1986 | DAC | A delay test system for high speed logic LSI's. | Kuniaki Kishida, F. Shirotori, Y. Ikemoto, Shun Ishiyama, Terumine Hayashi |