| 2017 | ETS | Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions. | Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue, Alex Orailoglu |
| 2016 | ETS | Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC. | Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue |
| 2015 | ETS | An ECC-based memory architecture with online self-repair capabilities for reliability enhancement. | Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato |
| 2014 | FPGA | Memory block based scan-BIST architecture for application-dependent FPGA testing. | Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue |
| 2012 | ITC | DART: Dependable VLSI test architecture and its implementation. | Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura |
| 2012 | ITC | A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation. | Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue |
| 2011 | ETS | Temperature-Variation-Aware Test Pattern Optimization. | Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara |
| 2011 | ITC | Faster-than-at-speed test for increased test quality and in-field reliability. | Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara |
| 2010 | ETS | Test pattern selection to optimize delay test quality with a limited size of test set. | Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara |
| 2010 | IOLTS | Aging test strategy and adaptive test scheduling for SoC failure prediction. | Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara |
| 2010 | VTS | Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. | Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara |
| 2009 | ASPDAC | Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. | Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara |
| 2009 | ETS | Partial Scan Approach for Secret Information Protection. | Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara |
| 2008 | DATE | Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. | Tomokazu Yoneda, Hideo Fujiwara |
| 2007 | ASPDAC | Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. | Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara |
| 2007 | DAC | A DFT Method for Time Expansion Model at Register Transfer Level. | Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara |
| 2007 | DATE | Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. | Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara |
| 2007 | ETS | Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. | Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara |
| 2007 | ISCAS | Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing. | Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara |
| 2007 | VTS | TAM Design and Optimization for Transparency-Based SoC Test. | Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara |
| 2007 | VTS | Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. | Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara |
| 2006 | ASPDAC | A memory grouping method for sharing memory BIST logic. | Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara |
| 2006 | DATE | Power-constrained test scheduling for multi-clock domain SoCs. | Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara |
| 2006 | ICCD | Power-Constrained SOC Test Schedules through Utilization of Functional Buses. | Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara |
| 2004 | ETS | An efficient scan tree design for test time reduction. | Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard |
| 2003 | ITC | Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability. | Tomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara |
| 2003 | VTS | Design for Consecutive Transparency of Cores in System-on-a-Chip. | Tomokazu Yoneda, Hideo Fujiwara |