Walter Stechele
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
65
Venues
25
Active years
2000–2025
Best venue rank
A*
Where they publish
- ADATE12 papers
- BFPL8 papers
- BGI6 papers
- CDSD5 papers
- A*CVPR4 papers
- A*DAC4 papers
- A*ICRA3 papers
- CIOLTS3 papers
- AGECCO2 papers
- AISLPED2 papers
- CDDECS2 papers
- AWACV1 paper
- ABMVC1 paper
- BICAART1 paper
- CICMLA1 paper
- AICCAD1 paper
- NationalKI1 paper
- CVCIP1 paper
- CECMS1 paper
- CISM1 paper
- BASPDAC1 paper
- BAVSS1 paper
- CISORC1 paper
- BDCC1 paper
- CISCAS1 paper
Papers
65 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | CVPR | RepFC: Universal Structural Reparametrization Block for High Performance, Lightweight Deep Neural Networks. | Shambhavi Balamuthu Sampath, Judeson Anthony Fernando, Moritz Thoma, Nael Fasfous, Lukas Frickenstein, Pierpaolo Mor, Manoj Rohit Vemparala, Alexander Frickenstein, Ulf Schlichtmann, Walter Stechele |
| 2025 | DAC | LA-MTL: Latency-Aware Automated Multi-Task Learning. | Shambhavi Balamuthu Sampath, Sami Sawani, Moritz Thoma, Lukas Frickenstein, Pierpaolo Mor, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Ulf Schlichtmann, Claudio Passerone, Walter Stechele |
| 2025 | DATE | HiFi-SAGE: High Fidelity GraphSAGE-Based Latency Estimators for DNN Optimization. | Shambhavi Balamuthu Sampath, Leon Hecht, Moritz Thoma, Lukas Frickenstein, Pierpaolo Mor, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone |
| 2024 | CVPR | Pruning as a Binarization Technique. | Lukas Frickenstein, Pierpaolo Mor, Shambhavi Balamuthu Sampath, Moritz Thoma, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Christian Unger, Claudio Passerone, Walter Stechele |
| 2024 | DATE | MATAR: Multi-Quantization-Aware Training for Accurate and Fast Hardware Retargeting. | Pierpaolo Mor, Moritz Thoma, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone |
| 2024 | WACV | Wino Vidi Vici: Conquering Numerical Instability of 8-bit Winograd Convolution for Accurate Inference Acceleration on Edge. | Pierpaolo Mor, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Moritz Thoma, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Christian Unger, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone |
| 2023 | DAC | WinoTrain: Winograd-Aware Training for Accurate Full 8-bit Convolution Acceleration. | Pierpaolo Mor, Shambhavi Balamuthu Sampath, Lukas Frickenstein, Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Walter Stechele, Claudio Passerone |
| 2022 | DAC | Accelerating and pruning CNNs for semantic segmentation on FPGA. | Pierpaolo Mor, Manoj Rohit Vemparala, Nael Fasfous, Saptarshi Mitra, Sreetama Sarkar, Alexander Frickenstein, Lukas Frickenstein, Domenik Helms, Naveen Shankar Nagaraja, Walter Stechele, Claudio Passerone |
| 2022 | DATE | Mind the Scaling Factors: Resilience Analysis of Quantized Adversarially Robust CNNs. | Nael Fasfous, Lukas Frickenstein, Michael Neumeier, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Maurizio Martina, Walter Stechele |
| 2022 | DATE | AnaCoNGA: Analytical HW-CNN Co-Design Using Nested Genetic Algorithms. | Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Driton Salihu, Julian Hfer, Anmol Singh, Naveen Shankar Nagaraja, Hans-Jrg Vgel, Nguyen Anh Vu Doan, Maurizio Martina, Jrgen Becker, Walter Stechele |
| 2022 | GECCO | Region of interest based non-dominated sorting genetic algorithm-II: an invite and conquer approach. | Manu Manuel, Benjamin Hien, Simon Conrady, Arne Kreddig, Nguyen Anh Vu Doan, Walter Stechele |
| 2021 | BMVC | Hardware-Aware Mixed-Precision Neural Networks using In-Train Quantization. | Manoj Rohit Vemparala, Nael Fasfous, Lukas Frickenstein, Alexander Frickenstein, Anmol Singh, Driton Salihu, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele |
| 2021 | CVPR | Adversarial Robust Model Compression Using In-Train Pruning. | Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Sreetama Sarkar, Qi Zhao, Sabine Kuhn, Lukas Frickenstein, Anmol Singh, Christian Unger, Naveen Shankar Nagaraja, Christian Wressnegger, Walter Stechele |
| 2021 | DSD | A Framework for Hardware-Accelerated Design Space Exploration for Approximate Computing on FPGA. | Arne Kreddig, Simon Conrady, Manu Manuel, Walter Stechele |
| 2021 | ICAART | Sensor Fusion Neural Networks for Gesture Recognition on Low-power Edge Devices. | Gbor Balzs, Mateusz Chmurski, Walter Stechele, Mariusz Zubert |
| 2021 | ICRA | Binary-LoRAX: Low-Latency Runtime Adaptable XNOR Classifier for Semi-Autonomous Grasping with Prosthetic Hands. | Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Mohamed Badawy, Felix Hundhausen, Julian Hfer, Naveen Shankar Nagaraja, Christian Unger, Hans-Jrg Vgel, Jrgen Becker, Tamim Asfour, Walter Stechele |
| 2020 | DAC | ALF: Autoencoder-based Low-rank Filter-sharing for Efficient Convolutional Neural Networks. | Alexander Frickenstein, Manoj Rohit Vemparala, Nael Fasfous, Laura Hauenschild, Naveen Shankar Nagaraja, Christian Unger, Walter Stechele |
| 2020 | DATE | OrthrusPE: Runtime Reconfigurable Processing Elements for Binary Neural Networks. | Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele |
| 2020 | ICMLA | Neural Architecture Search for Automotive Grid Fusion Networks Under Embedded Hardware Constraints. | Gbor Balzs, Walter Stechele |
| 2020 | ICRA | Binary DAD-Net: Binarized Driveable Area Detection Network for Autonomous Driving. | Alexander Frickenstein, Manoj Rohit Vemparala, Jakob Mayr, Naveen Shankar Nagaraja, Christian Unger, Federico Tombari, Walter Stechele |
| 2019 | CVPR | DSC: Dense-Sparse Convolution for Vectorized Inference of Convolutional Neural Networks. | Alexander Frickenstein, Manoj Rohit Vemparala, Christian Unger, Fatih Ayar, Walter Stechele |
| 2019 | GECCO | LCS-based automatic configuration of approximate computing parameters for FPGA system designs. | Simon Conrady, Manu Manuel, Arne Kreddig, Walter Stechele |
| 2019 | ICRA | Mixed Frame-/Event-Driven Fast Pedestrian Detection. | Zhuangyi Jiang, Pengfei Xia, Kai Huang, Walter Stechele, Guang Chen, Zhenshan Bing, Alois C. Knoll |
| 2018 | ICCAD | Efficient hardware acceleration of CNNs using logarithmic data representation with arbitrary log-base. | Sebastian Vogel, Mengyu Liang, Andre Guntoro, Walter Stechele, Gerd Ascheid |
| 2017 | KI | Online Multi-object Tracking-by-Clustering for Intelligent Transportation System with Neuromorphic Vision Sensor. | Gereon Hinz, Guang Chen, Muhammad Aafaque, Florian Rhrbein, Jrg Conradt, Zhenshan Bing, Zhongnan Qu, Walter Stechele, Alois C. Knoll |
| 2016 | FPL | Preface. | Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele |
| 2016 | IOLTS | Tackling long duration transients in sequential logic. | Erol Koser, Walter Stechele |
| 2015 | DSD | Matching Detection and Correction Schemes for Soft Error Handling in Sequential Logic. | Erol Koser, Felix Miller, Walter Stechele |
| 2015 | ISLPED | Design of fine-grained sequential approximate circuits using probability-aware fault emulation. | David May, Walter Stechele |
| 2014 | IOLTS | Towards low-cost fault detection strategy of FPGA configuration memory in real-time systems. | Michael Frischke, Andreas J. Rohatschek, Walter Stechele |
| 2014 | IOLTS | Improving the significance of probabilistic circuit fault emulations. | David May, Walter Stechele |
| 2014 | VCIP | Automatic denoising parameter estimation using gradient histograms. | Tamara Seybold, Florian Kuhn, Julian Habigt, Mark Hartenstein, Walter Stechele |
| 2013 | DSD | Dynamic Noise Estimation Approach for X-Ray Detectors on FPGAs. | Florian Aschauer, Walter Stechele, Johannes Treis |
| 2013 | DSD | FPGA Based Real-Time Data Processing DAQ System for the Mercury Imaging X-Ray Spectrometer. | Florian Aschauer, Walter Stechele, Johannes Treis |
| 2013 | ECMS | A Design Space Exploration Framework For Automotive Embedded Systems And Their Power Management. | Gregor Walla, Zaur Molotnikov, Hans-Ulrich Michel, Walter Stechele, Andreas Barthels, Andreas Herkersdorf |
| 2013 | FPL | Weighted partitioning of sequential processing chains for dynamically reconfigurable FPGAS. | Michael Feilen, Andreas Iliopoulos, Michael Vonbun, Walter Stechele |
| 2013 | FPL | A resource-efficient probabilistic fault simulator. | David May, Walter Stechele |
| 2013 | GI | Self-reconfigurable Control Architecture for Complex Robots. | Jan Hartmann, Walter Stechele, Erik Maehle |
| 2013 | GI | Potentials and Challenges for Multi-Core Processors in Robotic Applications. | Andreas Herkersdorf, Johny Paul, Ravi Kumar Pujari, Walter Stechele, Stefan Wallentowitz, Thomas Wild, Aurang Zaib |
| 2013 | ISM | Towards an Evaluation of Denoising Algorithms with Respect to Realistic Camera Noise. | Tamara Seybold, Christian Keimel, Marion Knopp, Walter Stechele |
| 2012 | ASPDAC | Invasive Computing for robotic vision. | Johny Paul, Walter Stechele, Manfred Krhnert, Tamim Asfour, Rdiger Dillmann |
| 2012 | DDECS | A low-overhead monitoring ring interconnect for MPSoC parameter optimization. | Abdelmajid Bouajila, Abdallah Lakhtel, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf |
| 2012 | FPL | Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources. | Michael Feilen, Matthias Ihmig, Christian Schwarzbauer, Walter Stechele |
| 2011 | DDECS | An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. | Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf |
| 2010 | AVSS | Subjective Logic Based Hybrid Approach to Conditional Evidence Fusion for Forensic Visual Surveillance. | Seunghan Han, Bonjung Koo, Andreas Hutter, Vinay D. Shet, Walter Stechele |
| 2010 | DATE | A rapid prototyping system for error-resilient multi-processor systems-on-chip. | Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jrgen Teich |
| 2010 | DSD | Architectural Vulnerability Factor Estimation with Backwards Analysis. | Robert Hartl, Andreas J. Rohatschek, Walter Stechele, Andreas Herkersdorf |
| 2010 | ISORC | Towards Scalability and Reliability of Autonomic Systems on Chip. | Johannes Zeppenfeld, Abdelmajid Bouajila, Andreas Herkersdorf, Walter Stechele |
| 2009 | FPL | Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation. | Christopher Claus, Robert Huitl, Joachim Rausch, Walter Stechele |
| 2008 | DATE | Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments. | Nicolas Alt, Christopher Claus, Walter Stechele |
| 2008 | DATE | Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. | Jrgen Becker, Michael Hbner, Robert Esser, Andreas Herkersdorf, Walter Stechele, Vera Lauer |
| 2008 | FPL | Fine grain reconfigurable architectures. | Josef Angermeier, Mateusz Majer, Jrgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hbner, Jrgen Becker, Enno Lbbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker |
| 2008 | FPL | A comparison of embedded reconfigurable video-processing architectures. | Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jrgen Teich |
| 2008 | FPL | A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. | Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hbner, Jrgen Becker |
| 2008 | GI | Workshop "Adaptive and Organic Systems". | Andreas Herkersdorf, Walter Stechele, Christian Mller-Schloer, Hartmut Schmeck |
| 2008 | GI | Learning Classifier Tables for Autonomic Systems on Chip. | Johannes Zeppenfeld, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf |
| 2007 | DATE | Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system. | Christopher Claus, Johannes Zeppenfeld, Florian Helmut Mller, Walter Stechele |
| 2006 | DATE | AutoVision: flexible processor architecture for video-assisted driving. | Andreas Herkersdorf, Walter Stechele |
| 2006 | GI | An Architecture for Runtime Evaluation of SoC Reliability. | Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf |
| 2005 | DATE | A Coprocessor for Accelerating Visual Information Processing. | Walter Stechele, L. Alvado Crcel, Stephan Herrmann, J. Lidn Simn |
| 2005 | DATE | Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization. | Paul Zuber, Armin Windschiegl, Ral Medina Beltrn de Otlora, Walter Stechele, Andreas Herkersdorf |
| 2005 | GI | Optimization Potential of CMOS Power by Wire Spacing. | Paul Zuber, Florian Helmut Mller, Walter Stechele |
| 2002 | DCC | MPEG-7 Binary Format for XML Dat. | Ulrich Niedermeier, Jrg Heuer, Andreas Hutter, Walter Stechele |
| 2002 | ISLPED | Novel modeling techniques for RTL power estimation. | Michael Eiermann, Walter Stechele |
| 2000 | ISCAS | A coprocessor architecture implementing the MPEG-4 visual core profile for mobile multimedia applications. | Andreas Hutter, Georg Giebel, Walter Stechele |