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Wu-Tung Cheng

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

81

Venues

10

Active years

1985–2025

Best venue rank

A*

Where they publish

Papers

81 indexed papers, newest first.

YearVenueTitleAuthors
2025ITCUsing Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects.Wu-Tung Cheng, Manish Sharma, Artur Stelmach, Jakub Janicki, Preston McWithey, Gaurav Veda, Szczepan Urban, Jayant D'Souza
2025VTSAPT: Optimal Tree for Diagnosis Simulation.Wu-Tung Cheng
2025VTSInnovation Practices Track: Frontiers in Diagnosis and Debug.Suriyaprakash Natarajan, Saghir A. Shaikh, Wu-Tung Cheng, Sankaran Menon
2024ITCAdaptive Diagnosis Points for 100% Chain Diagnosis Coverage.Wu-Tung Cheng, Manish Sharma, Xin Yang, Artur Stelmach, Szczepan Urban, Jakub Janicki, Preston McWithey
2022ITCIndustry Evaluation of Reversible Scan Chain Diagnosis.Soumya Mittal, Szczepan Urban, Kun Young Chung, Jakub Janicki, Wu-Tung Cheng, Martin Parley, Manish Sharma, Shaun Nicholson
2022VTSAccurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations.Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy
2020ETSEfficient Prognostication of Pattern Count with Different Input Compression Ratios.Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski
2020ITCPrediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations.Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada
2019ASPDACImproving scan chain diagnostic accuracy using multi-stage artificial neural networks.Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Hans Tsai, Wu-Tung Cheng
2019ETSA supervised machine learning application in volume diagnosis.Yue Tian, Gaurav Veda, Wu-Tung Cheng, Manish Sharma, Huaxing Tang, Neerja Bawaskar, Sudhakar M. Reddy
2019VTSOn Cyclic Scan Integrity Tests for EDT-based Compression.Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
2017ETSVolume diagnosis data mining.Wu-Tung Cheng, Yue Tian, Sudhakar M. Reddy
2016ETSTesting of small delay faults in a clock network.Shaofu Yang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2016ITCOnline slack-time binning for IO-registered die-to-die interconnects.Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng
2015DATEFeedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects.Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Hans Tsai, Wu-Tung Cheng
2015ETSAdvancements in diagnosis driven yield analysis (DDYA): A survey of state-of-the-art scan diagnosis and yield analysis technologies.Yu Huang, Wu Yang, Wu-Tung Cheng
2015ITCMonitoring the delay of long interconnects via distributed TDC.Meng-Ting Tsai, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2015VLSIDEmbedded Tutorial ET2: Volume Diagnosis for Yield Improvement.Wu-Tung Cheng, Sudhakar M. Reddy
2014ETSOn-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs.Shi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng
2013IOLTSAt-speed BIST for interposer wires supporting on-the-spot diagnosis.Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng
2013ITCDelay testing and characterization of post-bond interposer wires in 2.5-D ICs.Shi-Yu Huang, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng
2013ITCEDT bandwidth management - Practical scenarios for large SoC designs.Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles
2013ITCDiagnosis and Layout Aware (DLA) scan chain stitching.Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
2013VTSDistributed dynamic partitioning based diagnosis of scan chain.Yu Huang, Xiaoxin Fan, Huaxing Tang, Manish Sharma, Wu-Tung Cheng, Brady Benware, Sudhakar M. Reddy
2012DACSmall delay testing for TSVs in 3-D ICs.Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai
2012ITCImproved volume diagnosis throughput using dynamic design partitioning.Xiaoxin Fan, Huaxing Tang, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Brady Benware
2012ITCA unified method for parametric fault characterization of post-bond TSVs.Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter
2011ITCDeterministic IDDQ diagnosis using a net activation based model.Andras Kun, Ralf Arnold, Peter Heinrich, Gwenol Maugard, Huaxing Tang, Wu-Tung Cheng
2011ITCA novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores.Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab
2010ASPDACEmulating and diagnosing IR-drop by using dynamic SDF.Ke Peng, Yu Huang, Ruifeng Guo, Wu-Tung Cheng, Mohammad Tehranipoor
2010ASPDACImproved weight assignment for logic switching activity during at-speed test pattern generation.Meng-Fan Wu, Hsin-Cheih Pan, Teng-Han Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng
2010ETSFull-circuit SPICE simulation based validation of dynamic delay estimation.Ke Peng, Yu Huang, Pinki Mallick, Wu-Tung Cheng, Mohammad Tehranipoor
2010ETSScan based speed-path debug for a microprocessor.Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, Ken Amstutz
2010ICCADA scalable quantitative measure of IR-drop effects for scan pattern generation.Meng-Fan Wu, Kun-Han Tsai, Wu-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Augusli Kifli
2010ITCCase study of scan chain diagnosis and PFA on a low yield wafer.Yu Huang, Brady Benware, Wu-Tung Cheng, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen
2010ITCTest cycle power optimization for scan-based designs.Kun-Han Tsai, Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Augusli Kifli
2009DATEImproving compressed test pattern generation for multiple scan chain failure diagnosis.Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy
2009ETSSpeed-Path Debug Using At-Speed Scan Test Patterns.Ruifeng Guo, Wu-Tung Cheng, Kun-Han Tsai
2008ETSDiagnose Multiple Stuck-at Scan Chain Faults.Yu Huang, Wu-Tung Cheng, Ruifeng Guo
2008ITCDetection and Diagnosis of Static Scan Cell Internal Defect.Ruifeng Guo, Liyang Lai, Yu Huang, Wu-Tung Cheng
2008ITCExtraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
2008ITCEfficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data.Manish Sharma, Brady Benware, Lei Ling, David Abercrombie, Lincoln Lee, Martin Keim, Huaxing Tang, Wu-Tung Cheng, Ting-Pu Tai, Yi-Jung Chang, Reinhart Lin, Albert Mann
2008VTSReducing Scan Shift Power at RTL.Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak
2008VTSAutomatic Test Pattern Generation for Interconnect Open Defects.Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
2007ITCA complete test set to diagnose scan chain failures.Ruifeng Guo, Yu Huang, Wu-Tung Cheng
2007ITCDiagnose compound scan chain and system logic defects.Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Will Hsu, Yuan-Shih Chen, Albert Mann
2007ITCInterconnect open defect diagnosis with minimal physical information.Chen Liu, Wei Zou, Sudhakar M. Reddy, Wu-Tung Cheng, Manish Sharma, Huaxing Tang
2007ITCFaster defect localization in nanometer technology based on defective cell diagnosis.Manish Sharma, Wu-Tung Cheng, Ting-Pu Tai, Y. S. Cheng, Will Hsu, Chen Liu, Sudhakar M. Reddy, Albert Mann
2007VTSSpeeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary.Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang
2006ITCSignature Based Diagnosis for Logic BIST.Wu-Tung Cheng, Manish Sharma, Thomas Rinderknecht, Liyang Lai, Chris Hill
2006ITCDiagnosis with Limited Failure Information.Yu Huang, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg, Will Hsu, Yuan-Shih Chen
2006ITCX-Press Compactor for 1000x Reduction of Test Data.Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
2006ITCImproving Transition Fault Test Pattern Quality through At-Speed Diagnosis.Nandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich
2006VLSIDOn Methods to Improve Location Based Logic Diagnosis.Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang
2005ASPDACUsing fault model relaxation to diagnose real scan chain defects.Yu Huang, Wu-Tung Cheng, Greg Crowell
2005ICCDHardware Ef.cient LBISTWith Complementary Weights.Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng
2005ITCFull-speed field-programmable memory BIST architecture.Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy
2005ITCCompressed pattern diagnosis for scan chain failures.Yu Huang, Wu-Tung Cheng, Janusz Rajski
2005ITCCompression mode diagnosis enables high volume monitoring diagnosis flow.Andreas Leininger, Peter Muhmenthaler, Wu-Tung Cheng, Nagesh Tamarapalli, Wu Yang, Kun-Han Hans Tsai
2005ITCX-filter: filtering unknowns from compacted test responses.Manish Sharma, Wu-Tung Cheng
2004DATEIntermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis.Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung
2004ITCLogic BIST with Scan Chain Segmentation.Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng
2004VLSIDAt-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories.Xiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee
2004VTSMemory BIST Using ESP.Xiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk
2004VTSLogic BIST Using Constrained Scan Cells.Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel
2003DACUsing embedded infrastructure IP for SOC post-silicon verification.Yu Huang, Wu-Tung Cheng
2003ITCSilicon Diagnosis.Wu-Tung Cheng
2003ITCStatistical Diagnosis for Intermittent Scan Chain Hold-Time Fault.Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung
2003ITCBIST for Deep Submicron ASIC Memories with High Performance Application.Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai
2002ITCOptimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan
2002VLSIDConstraint Driven Pin Mapping for Concurrent SOC Testing.Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy
2001ITCOn RTL scan design.Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy
2000VTSSIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration.Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy
1999ITCHigh time for high level ATPG.Wu-Tung Cheng
1996ITCA Universal Technique for Accelerating Simulation of Scan Test Patterns.Bejoy G. Oomman, Wu-Tung Cheng, John A. Waicukauski
1990DACProofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator.Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel
1990ITCDiagnosis for wiring interconnects.Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu
1989DACDifferential Fault Simulation - a Fast Method Using Minimal Memory.Wu-Tung Cheng, Meng-Lin Yu
1988DACSplit Circuit Model for Test Generation.Wu-Tung Cheng
1988ICCDThe BACK algorithm for sequential test generation.Wu-Tung Cheng
1985ITCMultiple-Fault Detection in Iterative Logic Arrays.Wu-Tung Cheng, Janak H. Patel