| 2019 | IOLTS | An Efficient SAT-Attack Algorithm Against Logic Encryption. | Yusuke Matsunaga, Masayoshi Yoshimura |
| 2015 | ASPDAC | Accelerating SAT-based Boolean matching for heterogeneous FPGAs using one-hot encoding and CEGAR technique. | Yusuke Matsunaga |
| 2014 | DATE | Synthesis algorithm of parallel index generation units. | Yusuke Matsunaga |
| 2012 | IOLTS | Neutron-induced soft error rate estimation for SRAM using PHITS. | Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2011 | IOLTS | A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits. | Taiga Takata, Yusuke Matsunaga |
| 2011 | IOLTS | Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. | Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2011 | ISLPED | Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. | Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga |
| 2010 | ASPDAC | Multi-operand adder synthesis on FPGAs using generalized parallel counters. | Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga |
| 2010 | FPGA | A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). | Taiga Takata, Yusuke Matsunaga |
| 2008 | ASPDAC | An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis. | Tsuyoshi Sadakata, Yusuke Matsunaga |
| 2008 | ASPDAC | Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs. | Taiga Takata, Yusuke Matsunaga |
| 2008 | ICCD | Synthesis of parallel prefix adders considering switching activities. | Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga |
| 2006 | ISCAS | A character size optimization technique for throughput enhancement of character projection lithography. | Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura |
| 2004 | ASPDAC | Enhancing the performance of multi-cycle path analysis in an industrial setting. | Hiroyuki Higuchi, Yusuke Matsunaga |
| 1998 | ICCAD | On accelerating pattern matching for technology mapping. | Yusuke Matsunaga |
| 1996 | DAC | A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines. | Hiroyuki Higuchi, Yusuke Matsunaga |
| 1996 | DAC | An Efficient Equivalence Checker for Combinational Circuits. | Yusuke Matsunaga |
| 1995 | ASPDAC | Implicit prime compatible generation for minimizing incompletely specified finite state machines. | Hiroyuki Higuchi, Yusuke Matsunaga |
| 1994 | ICCAD | LP based cell selection with constraints of timing, area, and power consumption. | Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita |
| 1993 | DAC | On Computing the Transitive Closure of a State Transition Relation. | Yusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton |
| 1991 | DAC | A Resynthesis Approach for Network Optimization. | Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita |
| 1991 | ICCAD | Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs. | Masahiro Fujita, Yusuke Matsunaga |
| 1990 | DAC | Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. | Hitomi Sato, Yoshihiro Yasue, Yusuke Matsunaga, Masahiro Fujita |
| 1990 | ICCAD | Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. | Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda |
| 1990 | ICCAD | Multi-Level Logic Minimization Across Latch Boundaries. | Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda |
| 1990 | ICCD | Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams. | Hitomi Sato, Norikazu Takahashi, Yusuke Matsunaga, Masahiro Fujita |
| 1989 | ICCAD | Multi-level logic optimization using binary decision diagrams. | Yusuke Matsunaga, Masahiro Fujita |