| 2009 | Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. | Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara |
| 2009 | A multiple supply voltage based power reduction method in 3-D ICs considering process variations and thermal effects. | Shih-An Yu, Pei-Yu Huang, Yu-Min Lee |
| 2009 | Fast false path identification based on functional unsensitizability using RTL information. | Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara |
| 2009 | Analyzing and optimizing energy efficiency of algorithms on DVS systems a first step towards algorithmic energy minimization. | Tetsuo Yokoyama, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada |
| 2009 | Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement. | Yu-Wei Yang, Katherine Shu-Min Li |
| 2009 | A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization. | Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang |
| 2009 | Detectability of internal bridging faults in scan chains. | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
| 2009 | IO connection assignment and RDL routing for flip-chip designs. | Jin-Tai Yan, Zhi-Wei Chen |
| 2009 | FastRoute 4.0: global router with efficient via minimization. | Yue Xu, Yanheng Zhang, Chris Chu |
| 2009 | Computation and data transfer co-scheduling for interconnection bus minimization. | Cathy Qun Xu, Chun Jason Xue, Bessie C. Hu, Edwin Hsing-Mean Sha |
| 2009 | Bound-based identification of timing-violating paths under variability. | Lin Xie, Azadeh Davoodi |
| 2009 | Analog placement with common centroid and 1-D symmetry constraints. | Linfu Xiao, Evangeline F. Y. Young |
| 2009 | SAT-controlled redundancy addition and removal: a novel circuit restructuring technique. | Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, Chung-Yang Huang |
| 2009 | Risk aversion min-period retiming under process variations. | Jia Wang, Hai Zhou |
| 2009 | Exploring adjacency in floorplanning. | Jia Wang, Hai Zhou |
| 2009 | Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling. | Hai Wang, Hao Yu, Sheldon X.-D. Tan |
| 2009 | Variation-aware resource sharing and binding in behavioral synthesis. | Feng Wang, Yuan Xie, Andrs Takach |
| 2009 | Signal skew aware floorplanning and bumper signal assignment technique for flip-chip. | Cheng-Yu Wang, Wai-Kei Mak |
| 2009 | CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. | Chin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo |
| 2009 | Hybrid LZA: a near optimal implementation of the leading zero anticipator. | Amit Verma, Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2009 | A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. | Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya |
| 2009 | Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform. | Antonino Tumeo, Marco Branca, Lorenzo Camerini, Marco Ceriani, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto |
| 2009 | Needs and trends in embedded software development for consumer electronics. | Yasutaka Tsunakawa |
| 2009 | A full-synthesizable high-precision built-in delay time measurement circuit. | Ming-Chien Tsai, Ching-Hwa Cheng |
| 2009 | Exact and fast L1 cache simulation for embedded systems. | Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |