| 2009 | Automated design and optimization of circuits in emerging technologies. | Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil |
| 2009 | Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. | Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2009 | A UML-based approach for heterogeneous IP integration. | Zhenxin Sun, Weng-Fai Wong |
| 2009 | Aspects of GPU for general purpose high performance computing. | Reiji Suda, Takayuki Aoki, Shoichi Hirasawa, Akira Nukada, Hiroki Honda, Satoshi Matsuoka |
| 2009 | From restrictive to prescriptive design. | Leon Stok |
| 2009 | A criticality-driven microarchitectural three dimensional (3D) floorplanner. | Srinath Sridharan, Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan |
| 2009 | Incremental and on-demand random walk for iterative power distribution network analysis. | Yiyu Shi, Wei Yao, Jinjun Xiong, Lei He |
| 2009 | Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction. | Yiyu Shi, Jinjun Xiong, Howard Chen, Lei He |
| 2009 | A Time-to-Digital Converter with small circuitry. | Kazuya Shimizu, Masato Kaneta, HaiJun Lin, Haruo Kobayashi, Nobukazu Takai, Masao Hotta |
| 2009 | A 52-mW 8.29mm | Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu |
| 2009 | Novel task migration framework on configurable heterogeneous MPSoC platforms. | Hao Shen, Frdric Ptrot |
| 2009 | Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. | Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong |
| 2009 | An inductor-less MPPT design for light energy harvesting systems. | Hui Shao, Chi-Ying Tsui, Wing-Hung Ki |
| 2009 | Low energy level converter design for sub-V | Hui Shao, Chi-Ying Tsui |
| 2009 | An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture. | Daisaku Seto, Minoru Watanabe |
| 2009 | A cycle-based synthesis algorithm for reversible logic. | Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani |
| 2009 | Addressing thermal and power delivery bottlenecks in 3D circuits. | Sachin S. Sapatnekar |
| 2009 | System-level process variability compensation on memory organizations: on the scalability of multi-mode memories. | Concepcin Sanz, Manuel Prieto, Jos Ignacio Gmez, Antonis Papanikolaou, Francky Catthoor |
| 2009 | Dependable VLSI: device, design and architecture: how should they cooperate? | Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe |
| 2009 | Challenges to EDA system from the view point of processor design and technology drivers. | Mitsuo Saito |
| 2009 | Automated synthesis and verification of embedded systems: wishful thinking or reality? | Wolfgang Rosenstiel |
| 2009 | High-speed low-power FinFET based domino logic. | Seid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee |
| 2009 | Analysis of communication delay bounds for network on chips. | Yue Qian, Zhonghai Lu, Wenhua Dou |
| 2009 | Flexible and abstract communication and interconnect modeling for MPSoC. | Katalin Popovici, Ahmed Amine Jerraya |
| 2009 | Dynamic test compaction for a random test generation procedure with input cube avoidance. | Irith Pomeranz, Sudhakar M. Reddy |