| 2009 | Parallel transistor level circuit simulation using domain decomposition methods. | He Peng, Chung-Kuan Cheng |
| 2009 | Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications. | Sudeep Pasricha, Nikil D. Dutt, Fadi J. Kurdahi |
| 2009 | Variability-aware robust design space exploration of chip multiprocessor architectures. | Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria |
| 2009 | A V | H. Oshiyama, Toshihiro Matsuda, K. Suzuki, Hideyuki Iwata, Takashi Ohzone |
| 2009 | Low-power CMOS transceiver circuits for 60GHz band millimeter-wave impulse radio. | Ahmet nc, Minoru Fujishima |
| 2009 | UniPhier: series development and SoC management. | Yoshito Nishimichi, Nobuo Higaki, Masataka Osaka, Seiji Horii, Hisato Yoshida |
| 2009 | Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture. | Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa, Toru Fujihira, Kenichi Iwata, Motoki Kimura, Fumitaka Izuhara, Seiji Mochizuki, Masaki Nobori |
| 2009 | Synthesis of networks on chips for 3D systems on chips. | Srinivasan Murali, Ciprian Seiculescu, Luca Benini, Giovanni De Micheli |
| 2009 | A 3D prototyping chip based on a wafer-level stacking technology. | Nobuaki Miyakawa |
| 2009 | Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations. | Mesut Meterelliyoz, Kaushik Roy |
| 2009 | An optimized design for serial-parallel finite field multiplication over | Pramod Kumar Meher, Yajun Ha, Chiou-Yng Lee |
| 2009 | A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. | Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiroaki Honda, Koji Inoue, Kazuaki J. Murakami |
| 2009 | Design methods for pipeline & delta-sigma A-to-D converters with convex optimization. | Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho |
| 2009 | On using SAT to ordered escape problems. | Lijuan Luo, Martin D. F. Wong |
| 2009 | FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization. | Gregory Lucas, Scott Cromar, Deming Chen |
| 2009 | Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model. | Chen Kang Lo, Ren-Song Tsay |
| 2009 | Multi-clock SVA synthesis without re-writing. | Jiang Long, Andrew Seawright, Paparao Kavalipati |
| 2009 | Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis. | Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee |
| 2009 | Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit. | Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya |
| 2009 | A 100Mbps, 0.19mW asynchronous threshold detector with DC power-free pulse discrimination for impulse UWB receiver. | Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai |
| 2009 | Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture. | Bao Liu |
| 2009 | Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method. | Duo Li, Sheldon X.-D. Tan, Gengsheng Chen, Xuan Zeng |
| 2009 | Dependent latch identification in the reachable state space. | Chen-Hsuan Lin, Chun-Yao Wang |
| 2009 | An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective. | Jing Li, Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik Roy |
| 2009 | A novel thermal optimization flow using incremental floorplanning for 3D ICs. | Xin Li, Yuchun Ma, Xianlong Hong |