| 2017 | Rapid growth of IP traffic is driving adoption of silicon photonics in data centers. | Kaushik Patel |
| 2017 | DAC: Dedup-assisted compression scheme for improving lifetime of NAND storage systems. | Jisung Park, Sungjin Lee, Jihong Kim |
| 2017 | Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions. | Chenyun Pan, Azad Naeemi |
| 2017 | Semantic driven hierarchical learning for energy-efficient image classification. | Priyadarshini Panda, Kaushik Roy |
| 2017 | Ultra low-power visual odometry for nano-scale unmanned aerial vehicles. | Daniele Palossi, Andrea Marongiu, Luca Benini |
| 2017 | A methodology for the design of dynamic accuracy operators by runtime back bias. | Daniele Jahier Pagliari, Yves Durand, David Coriat, Anca Molnos, Edith Beign, Enrico Macii, Massimo Poncino |
| 2017 | An optimal approach for low-power migraine prediction models in the state-of-the-art wireless monitoring devices. | Josu Pagn, Ramin Fallahzadeh, Hassan Ghasemzadeh, Jos Manuel Moya, Jos Luis Risco-Martn, Jos L. Ayala |
| 2017 | Context-sensitive timing automata for fast source level simulation. | Sebastian Ottlik, Christoph Gerum, Alexander Viehl, Wolfgang Rosenstiel, Oliver Bringmann |
| 2017 | Simulation-based design procedure for sub 1V CMOS current reference. | Dmitry Osipov, Steffen Paul |
| 2017 | Towards exascale computing with heterogeneous architectures. | Kenneth O'Brien, Lorenzo Di Tucci, Gianluca Durelli, Michaela Blott |
| 2017 | Mixed-criticality processing pipelines. | Dionisio de Niz, Bjrn Andersson, Hyoseung Kim, Mark H. Klein, Linh Thi Xuan Phan, Raj Rajkumar |
| 2017 | A novel way to efficiently simulate complex full systems incorporating hardware accelerators. | Nikolaos Tampouratzis, Konstantinos Georgopoulos, Yannis Papaefstathiou |
| 2017 | Automatic construction of models for analytic system-level design space exploration problems. | Seyed-Hosein Attarzadeh-Niaki, Ingo Sander |
| 2017 | Double MAC: Doubling the performance of convolutional neural networks on modern FPGAs. | Dong Nguyen, Daewoo Kim, Jongeun Lee |
| 2017 | Framework for quantifying and managing accuracy in stochastic circuit design. | Florian Neugebauer, Ilia Polian, John P. Hayes |
| 2017 | Enhancing symbolic system synthesis through ASPmT with partial assignment evaluation. | Kai Neubauer, Philipp Wanko, Torsten Schaub, Christian Haubelt |
| 2017 | Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation. | Taesik Na, Jong Hwan Ko, Saibal Mukhopadhyay |
| 2017 | VAET-STT: A variation aware estimator tool for STT-MRAM based memories. | Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Mehdi Baradaran Tahoori |
| 2017 | Simulating preemptive scheduling with timing-aware blocks in Simulink. | Andreas Naderlinger |
| 2017 | The RowHammer problem and other issues we may face as memory becomes denser. | Onur Mutlu |
| 2017 | Quantifying error: Extending static timing analysis with probabilistic transitions. | Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides |
| 2017 | EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. | Vojtech Mrazek, Radek Hrbacek, Zdenek Vascek, Luks Sekanina |
| 2017 | A new method to identify threshold logic functions. | Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis |
| 2017 | Superword level parallelism aware word length optimization. | Ali Hassan El Moussawi, Steven Derrien |
| 2017 | Reliability assessment of fault tolerant routing algorithms in networks-on-chip: An analytic approach. | Sadia Moriam, Gerhard P. Fettweis |