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Design, Automation and Test in Europe Conference

DATE

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering · Software Engineering

Papers indexed

9,217

1995–2026

Papers per year

1995445 peak2026

DATE papers

9,217 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2015Energy-efficient cache design in emerging mobile platforms: the implications and optimizations.Kaige Yan, Xin Fu
2015Formal consistency checking over specifications in natural languages.Rongjie Yan, Chih-Hong Cheng, Yesheng Chai
2015Comparison of multi-purpose cores of Keccak and AES.Panasayya Yalla, Ekawat Homsirikamol, Jens-Peter Kaps
2015Efficiency-driven design time optimization of a hybrid energy storage system with networked charge transfer interconnect.Qing Xie, Younghyun Kim, Donkyu Baek, Yanzhi Wang, Massoud Pedram, Naehyuck Chang
2015Using structural relations for checking combinationality of cyclic circuits.Wan-Chen Weng, Yung-Chih Chen, Jui-Hung Chen, Ching-Yi Huang, Chun-Yao Wang
2015Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs.Christian Weis, Matthias Jung, Peter Ehses, Cristiano Santos, Pascal Vivet, Sven Goossens, Martijn Koedam, Norbert Wehn
2015A universal macro block mapping scheme for arithmetic circuits.Xing Wei, Yi Diao, Tak-Kei Lam, Yu-Liang Wu
2015A scalable and high-density FPGA architecture with multi-level phase change memory.Chunan Wei, Ashutosh Dhar, Deming Chen
2015Timing analysis of an avionics case study on complex hardware/software platforms.Franck Wartel, Leonidas Kosmidis, Adriana Gogonel, Andrea Baldovin, Zo R. Stephenson, Benoit Triquet, Eduardo Quiones, Code Lo, Enrico Mezzetti, Ian Broster, Jaume Abella, Liliana Cucu-Grosjean, Tullio Vardanega, Francisco J. Cazorla
2015A re-entrant flowshop heuristic for online scheduling of the paper path in a large scale printer.Umar Waqas, Marc Geilen, Jack Kandelaars, Lou J. Somers, Twan Basten, Sander Stuijk, Patrick Vestjens, Henk Corporaal
2015Adaptively tolerate power-gating-induced power/ground noise under process variations.Zhe Wang, Xuan Wang, Jiang Xu, Xiaowen Wu, Zhehui Wang, Peng Yang, Luan H. K. Duong, Haoran Li, Rafael Kioji Vivas Maeda, Zhifei Wang
2015Multi-core fixed-priority scheduling of real-time tasks with statistical deadline guarantee.Tianyi Wang, Linwei Niu, Shaolei Ren, Gang Quan
2015SODA: software defined FPGA based accelerators for big data.Chao Wang, Xi Li, Xuehai Zhou
2015Eliminating intra-warp conflict misses in GPU.Bin Wang, Zhuo Liu, Xinning Wang, Weikuan Yu
2015An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognition.Yuhao Wang, Hantao Huang, Leibin Ni, Hao Yu, Mei Yan, Chuliang Weng, Wei Yang, Junfeng Zhao
2015A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics.Arunkumar Vijayakumar, Sandip Kundu
2015NFRs early estimation through software metrics.Andrws Vieira, Pedro Faustini, Luigi Carro, rika F. Cota
2015Spintastic: <u>spin</u>-based s<u>t</u>och<u>astic</u> logic for energy-efficient computing.Rangharajan Venkatesan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan
2015Designing inexact systems efficiently using elimination heuristics.Shyamsundar Venkataraman, Akash Kumar, Jeremy Schlachter, Christian C. Enz
2015Computing approximately, and efficiently.Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
2015SAPPHIRE: an always-on context-aware computer vision system for portable devices.Swagath Venkataramani, Victor Bahl, Xian-Sheng Hua, Jie Liu, Jin Li, Matthai Philipose, Bodhi Priyantha, Mohammed Shoaib
2015Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell.Elena I. Vatajelu, Rosa Rodrguez-Montas, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras
2015STT MRAM-Based PUFs.Elena-Ioana Vatajelu, Giorgio Di Natale, Marco Indaco, Paolo Prinetto
2015OpenMP and timing predictability: a possible union?Roberto Vargas, Eduardo Quiones, Andrea Marongiu
2015RNA: a reconfigurable architecture for hardware neural acceleration.Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
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