| 2014 | Improving efficiency of extensible processors by using approximate custom instructions. | Mehdi Kamal, Amin Ghasemazar, Ali Afzali-Kusha, Massoud Pedram |
| 2014 | Co-optimization of memory BIST grouping, test scheduling, and logic placement. | Andrew B. Kahng, Ilgweon Kang |
| 2014 | A hybrid non-volatile SRAM cell with concurrent SEU detection and correction. | Pilin Junsangsri, Fabrizio Lombardi, Jie Han |
| 2014 | Scalable liveness verification for communication fabrics. | Sebastiaan J. C. Joosten, Julien Schmaltz |
| 2014 | Minimally buffered single-cycle deflection router. | Gnaneswara Rao Jonna, John Jose, Rachana Radhakrishnan, Madhu Mutyam |
| 2014 | Real-time trust evaluation in integrated circuits. | Yier Jin, Dean Sullivan |
| 2014 | EDA tools trust evaluation through security property proofs. | Yier Jin |
| 2014 | Mission profile aware IC design - A case study. | Goeran Jerke, Andrew B. Kahng |
| 2014 | Built-in self-test and characterization of polar transmitter parameters in the loop-back mode. | Jae Woong Jeong, Sule Ozev, Shreyas Sen, Vishwanath Natarajan, Mustapha Slamani |
| 2014 | Bus designs for time-probabilistic multicore processors. | Javier Jalle, Leonidas Kosmidis, Jaume Abella, Eduardo Quiones, Francisco J. Cazorla |
| 2014 | DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy. | Zoran Jaksic, Ramon Canal |
| 2014 | Attack-resilient sensor fusion. | Radoslav Ivanov, Miroslav Pajic, Insup Lee |
| 2014 | Bit-Flipping Scan - A unified architecture for fault tolerance and offline test. | Michael E. Imhof, Hans-Joachim Wunderlich |
| 2014 | Design of safety critical systems by refinement. | Alex Iliasov, Arseniy Alekseyev, Danil Sokolov, Andrey Mokhov |
| 2014 | Library-based scalable refinement checking for contract-based design. | Antonio Iannopollo, Pierluigi Nuzzo, Stavros Tripakis, Alberto L. Sangiovanni-Vincentelli |
| 2014 | Leveraging on-chip networks for efficient prediction on multicore coherence. | Libo Huang |
| 2014 | A high performance SEU-tolerant latch for nanoscale CMOS technology. | Zhengfeng Huang |
| 2014 | ArChiVED: Architectural checking via event digests for high performance validation. | Chang-Hong Hsu, Debapriya Chatterjee, Ronny Morad, Raviv Gal, Valeria Bertacco |
| 2014 | Wear-out analysis of Error Correction Techniques in Phase-Change Memory. | Caio Hoffman, Luiz Ramos, Rodolfo Azevedo, Guido Araujo |
| 2014 | Increasing the efficiency of syndrome coding for PUFs with helper data compression. | Matthias Hiller, Georg Sigl |
| 2014 | SuperRange: Wide operational range power delivery design for both STV and NTV computing. | Xin He, Guihai Yan, Yinhe Han, Xiaowei Li |
| 2014 | The energy benefit of level-crossing sampling including the actuator's energy consumption. | Burkhard Hensel, Klaus Kabitzsch |
| 2014 | Physical vulnerabilities of Physically Unclonable Functions. | Clemens Helfmeier, Christian Boit, Dmitry Nedospasov, Shahin Tajik, Jean-Pierre Seifert |
| 2014 | System integration - The bridge between More than Moore and More Moore. | Andy Heinig, Manfred Dietrich, Andreas Herkersdorf, Felix Miller, Thomas Wild, Kai Hahn, Armin Grnewald, Rainer Brck, Steffen Krohnert, Jochen Reisinger |
| 2014 | Modeling of an analog recording system design for ECoG and AP signals. | Nils Heidmann, Nico Hellwege, Tim Hohlein, Thomas Westphal, Dagmar Peters-Drolshagen, Steffen Paul |