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International Symposium on Design and Diagnostics of Electronic Circuits and Systems

DDECS

C

CORE rank

CORE rank (raw)

C

Fields of research

Computer Systems Engineering

Papers indexed

1,124

2006–2026

Papers per year

200691 peak2026

DDECS papers

1,124 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2021Efficient Neural Network Approximation via Bayesian Reasoning.Alessandro Savino, Marcello Traiola, Stefano Di Carlo, Alberto Bosio
2021High-speed stateful packet classifier based on TSS algorithm optimized for off-chip memories.Michal Orsk, Toms Benes
2021Approximate Multipliers for Optimal Utilization of FPGA Resources.Christoph Niemann, Michael Rethfeldt, Dirk Timmermann
2021EKV MOS Transistor Model For Ultra Low-Voltage Bulk-Driven IC Design.Luks Nagy, Daniel Arbet, Martin Kovc, Miroslav Potocn, Michal Sovcik, Viera Stopjakov
2021Enhanced Reliability of Fully Differential Difference Amplifier Through On-chip Digital Calibration.David Maljar, Michal Sovck, Daniel Arbet, Viera Stopjakov
2021A Model-Based Framework to Assess the Reliability of Safety-Critical Applications.Lucas Matana Luza, Annachiara Ruospo, Alberto Bosio, Ernesto Snchez, Luigi Dilillo
2021Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition.Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
2021Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel Array.Lukasz A. Kadlubowski, Piotr Kmon
2021An Open-source Library of Large Integer Polynomial Multipliers.Malik Imran, Zain Ul Abideen, Samuel Pagliarini
2021On the Functional Test of Special Function Units in GPUs.Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2021Embedded Test Instrument for Intermittent Resistive Fault Detection at Chip Level and Its Reuse at Board Level.Hassan Ebrahimi, Hans G. Kerkhoff
2021Prevention and Detection Methods of Systematic Failures in the Implementation of SoC Safety Mechanisms not Covered by Regular Functional Tests.Denis Dutey, Stephane Martin, Anne Merlande, Om Ranjan
2021PolyAdd: Polynomial Formal Verification of Adder Circuits.Rolf Drechsler
2021Fully-integrated SPAD active quenching/resetting circuit in high-voltage 0.35-μ m CMOS for reaching PDP saturation at 650 nm.Alija Dervic, Saman Kohneh Poushi, Horst Zimmermann
2021A Parameterizable Chisel Generator of Numerically Controlled Oscillators for Direct Digital Synthesis.Vukan D. Damnjanovic, Marija L. Petrovic, Vladimir M. Milovanovic
2021A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor Cores.Aleksa Damljanovic, Annachiara Ruospo, Ernesto Snchez, Giovanni Squillero
2021Predictive Fault Grouping based on Faulty AC Matrices.Nicola Dall'Ora, Sadia Azam, Enrico Fraccaroli, Andr Alberts, Franco Fummi
2021Emerging Technologies: Challenges and Opportunities for Logic Synthesis.Alberto Bosio, Mayeul Cantan, Cdric Marchand, Ian O'Connor, Petr Fiser, Arnaud Poittevin, Marcello Traiola
2021Q-Learning-based Routing Algorithm for 3D Network-on-Chips.Nurettin Blc, Suleyman Tosun
2021Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures.Davide Appello, Paolo Bernardi, Andrea Calabrese, Stefano Littardi, Giorgio Pollaccia, Stefano Quer, Vincenzo Tancorre, Roberto Ugioli
2020Characterization of Printed Humidity Sensor Based on Nanoparticle Copper Oxide.C. Zlebic, Ljiljana Zivanov, Nelu Blaz, Milica Kisic, Miloljub Lukovic
2020Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations.Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Zainalabedin Navabi
2020Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems.Julie Roux, Vincent Beroulle, Katell Morin-Allory, Rgis Leveugle, Lilian Bossuet, Frdric Czilly, Frdric Berthoz, Gilles Genvrier, Franois Cerisier
2020DiBA: n-Dimensional Bitslice Architecture for LSTM Implementation.Mahboobe Sadeghipour Roodsari, Mohamad Ali Saber, Zainalabedin Navabi
2020SHiLA: Synthesizing High-Level Assertions for High-Speed Validation of High-Level Designs.Mohammad Riazati, Masoud Daneshtalab, Mikael Sjdin, Bjrn Lisper
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