| 2011 | Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms. | Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, Ren Cumplido, Miguel Morales-Sandoval |
| 2011 | Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation. | Nima Aghaee, Zebo Peng, Petru Eles |
| 2011 | Mutant Fault Injection in Functional Properties of a Model to Improve Coverage Metrics. | Ali Abbasinasab, Mehdi Mohammadi, Siamak Mohammadi, Svetlana N. Yanushkevich, Michael Smith |
| 2010 | On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism. | Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen |
| 2010 | Static Average Case Power Estimation Technique for Block Ciphers. | Tingcong Ye, Dilip P. Vasudevan, Jiaoyan Chen, Emanuel M. Popovici, Michel P. Schellekens |
| 2010 | A Novel VLSI Architecture of Fixed-Complexity Sphere Decoder. | Bin Wu, Guido Masera |
| 2010 | A Programming Model and a NoC-Based Architecture for Streaming Applications. | Yun Jie Wu, Dominique Houzet, Sylvain Huet |
| 2010 | Software Programmable Data Allocation in Multi-bank Memory of SIMD Processors. | Jian Wang, Joar Sohl, Olof Kraigher, Dake Liu |
| 2010 | Medical Diagnosis Improvement Through Image Quality Enhancement Based on Super-Resolution. | Lara G. Villanueva, Gustavo M. Callic, Flix Tobajas, Sebastin Lpez, Valentin de Armas, Jos Francisco Lpez, Roberto Sarmiento |
| 2010 | Design of Trace-Based Split Array Caches for Embedded Applications. | Alice M. Tokarnia, Marina Tachibana |
| 2010 | Customizable Composition and Parameterization of Hardware Design Transformations. | Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides |
| 2010 | Computation Reduction Techniques for Vector Median Filtering and their Hardware Implementation. | Ozgur Tasdizen, Ilker Hamzaoglu |
| 2010 | Multiple Bit Error Detection and Correction in Memory. | J. F. Tarillo, Nikolaos Mavrogiannakis, Carlos Arthur Lang Lisba, Costas Argyrides, Luigi Carro |
| 2010 | Description-Level Optimisation of Synthesisable Asynchronous Circuits. | Luis A. Tarazona, Doug A. Edwards, Andrew Bardsley, Luis A. Plana |
| 2010 | Unified Digit Serial Systolic Montgomery Multiplication Architecture for Special Classes of Polynomials over GF(2m). | Somsubhra Talapatra, Hafizur Rahaman, Samir K. Saha |
| 2010 | A Class of Recursive Networks on a Chip for Enhancing Intercluster Parallelism. | Masaru Takesue |
| 2010 | Visualization of Multi-objective Design Space Exploration for Embedded Systems. | Toktam Taghavi, Andy D. Pimentel |
| 2010 | Dynamic Control Flow Checking Technique for Reliable Microprocessors. | Makoto Sugihara |
| 2010 | A Multicore SDR Architecture for Reconfigurable WiMAX Downlink. | Pedro Surez-Casal, Angel Carro-Lagoa, Jos Antonio Garca-Naya, Luis Castedo |
| 2010 | A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour. | Sander Stuijk, Marc Geilen, Twan Basten |
| 2010 | Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration. | Martin Straka, Jan Kastil, Zdenek Kotsek |
| 2010 | Network-on-Multi-Chip (NoMC) for Multi-FPGA Multimedia Systems. | Marta Stepniewska, Adam Luczak, Jakub Siast |
| 2010 | LEON3 ViP: A Virtual Platform with Fault Injection Capabilities. | Antonio da Silva, Sebastin Snchez |
| 2010 | Creation of Partial FPGA Configurations at Run-Time. | Miguel Lino Silva, Joo Canas Ferreira |
| 2010 | Reconfigurable Grid Alu Processor: Optimization and Design Space Exploration. | Basher Shehan, Ralf Jahr, Sascha Uhrig, Theo Ungerer |