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Euromicro Conference Series on Digital System Design

DSD

C

CORE rank

CORE rank (raw)

C

Fields of research

Computer Systems Engineering · Distributed Computing and Systems Software

Papers indexed

2,448

2001–2025

Papers per year

2001136 peak2025

DSD papers

2,448 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2010A Traffic Differentiation Add-On to the IEEE 802.15.4 Protocol: Implementation and Experimental Validation over a Real-Time Operating system.Ricardo Severino, Manish Batsa, Mrio Alves, Anis Koubaa
2010Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit.Bibhash Sen, Anik Sengupta, Mamata Dalui, Biplab K. Sikdar
2010On the Numbers of Variables to Represent Multi-valued Incompletely Specified Functions.Tsutomu Sasao
2010High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs.Rubn Salvador, Flix Moreno, Teresa Riesgo, Luks Sekanina
2010Power Distribution in NoCs Through a Fuzzy Based Selection Strategy for Adaptive Routing.Nastaran Salehi, Ahmad Khadem Zadeh, Arash Dana
2010Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications.Mostafa E. Salehi, Hamed Dorosti, Sied Mehdi Fakhraie
2010Storage-Aware Value Prediction.Mohammad Salehi, Amirali Baniasadi
2010Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance.Imtiaz Sajid, Sotirios G. Ziavras, Muhammad Mansoor Ahmed
2010A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems.Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Kunal P. Ghosh, Kavi Arya, Madhav P. Desai
2010Gracefully Degrading Circuit Controllers Based on Polytronics.Richard Ruzicka
2010An Approximate Maximum Common Subgraph Algorithm for Large Digital Circuits.Jochem H. Rutgers, Pascal T. Wolkotte, Philip K. F. Hlzenspies, Jan Kuper, Gerard J. M. Smit
2010Application Dependent FPGA Testing Method.Martin Rozkovec, Jiri Jencek, Ondrej Novk
2010A New High-Level Methodology for Programming FPGA-Based Smart Camera.Nicolas Roudel, Franois Berry, Jocelyn Srot, Laurent Eck
2010A Latency-Efficient Router Architecture for CMP Systems.Antoni Roca, Jos Flich, Federico Silla, Jos Duato
2010Simulation of High-Performance Memory Allocators.Jos Luis Risco-Martn, Jos Manuel Colmenar, David Atienza, Jos Ignacio Hidalgo
2010Multi-core Technology -- Next Evolution Step in Safety Critical Systems for Industrial Applications?Frank Reichenbach, Alexander Wold
2010Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGA.Adolfo Recio, Peter M. Athanas
2010Generated Cycle-Accurate Profiler for C Language.Zdenek Prikryl, Karel Masark, Toms Hruska, Adam Husr
2010On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels.Stanislaw J. Piestrak
2010A Test Bench for Distortion-Energy Optimization of a DSP-Based H.264/SVC Decoder.Fernando Pescador, Eduardo Jurez Martnez, David Samper Martnez, Csar Sanz, Mickal Raulet
2010An Efficient Method to Reliable Data Transmission in Network-on-Chips.Ahmad Patooghy, Hamed Tabkhi, Seyed Ghassem Miremadi
2010System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes.Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys
2010An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip.Maurizio Palesi, Rickard Holsmark, Xiaohang Wang, Shashi Kumar, Mei Yang, Yingtao Jiang, Vincenzo Catania
2010A Modular Peripheral to Support Self-Reconfiguration in SoCs.Andrs Otero, Angel Morales-Cas, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2010Evaluation of RTD-CMOS Logic Gates.Juan Nez, Maria J. Avedillo, Jos M. Quintana
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