| 2010 | In-channel Flow Control Scheme for Network-on-Chip. | Vrishali Vijay Nimbalkar, Kuruvilla Varghese |
| 2010 | A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip Networks. | Son Truong Nguyen, Shigeru Oyanagi |
| 2010 | A Common Operator for FFT and Viterbi Algorithms. | Malek Naoues, Laurent Alaus, Dominique Noguet |
| 2010 | A Packet Classifier Using a Parallel Branching Program Machine. | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura |
| 2010 | Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms. | Saad Mubeen, Shashi Kumar |
| 2010 | A Design Process for Hardware/Software System Co-design and its Application to Designing a Reconfigurable FPGA. | Flix Moreno, Ignacio Lpez, Ricardo Sanz |
| 2010 | A Parallel for Loop Memory Template for a High Level Synthesis Compiler. | Craig Moore, Wim Meeus, Harald Devos, Dirk Stroobandt |
| 2010 | Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. | Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman |
| 2010 | A Case for Hardware Task Management Support for the StarSS Programming Model. | Cor Meenderinck, Ben H. H. Juurlink |
| 2010 | Arithmetic Units for RNS Moduli {2n-3} and {2n+3} Operations. | Pedro Miguens Matutino, Ricardo Chaves, Leonel Sousa |
| 2010 | Evaluating OpenMP Support Costs on MPSoCs. | Andrea Marongiu, Paolo Burgio, Luca Benini |
| 2010 | An Improved Hardware Implementation of the Grain Stream Cipher. | Shohreh Sharif Mansouri, Elena Dubrova |
| 2010 | Path-Delay Fault Testing in Embedded Content Addressable Memories. | Palanichamy Manikandan, Bjrn B. Larsen, Einar J. Aas |
| 2010 | Adaptive Cache Memories for SMT Processors. | Sonia Lpez, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, Jos Ignacio Hidalgo |
| 2010 | An FPGA-Based Accelerator for Analog VLSI Artificial Neural Network Emulation. | Barend van Liempd, Daniel Herrera, Miguel E. Figueroa |
| 2010 | Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints. | Igor Lemberski, Petr Fiser |
| 2010 | Evaluating a Transmission Power Self-Optimization Technique for WSN in EMI Environments. | Felipe Lavratti, Alex R. Pinto, Letcia Maria Veiras Bolzani, Fabian Vargas, Carlos Barros Montez, Fernando Hernandez, Edmundo Gatti, C. Silva |
| 2010 | An Improved Automotive Multiple Target Tracking System Design. | Tobias Lange, Naim Harb, Haisheng Liu, Smal Niar, Rabie Ben Atitallah |
| 2010 | Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application. | Deepak Kumar, Pankaj Kumar, Manisha Pattanaik |
| 2010 | NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems. | Tim Kranich, Mladen Berekovic |
| 2010 | Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures. | Ren Kothe, Heinrich Theodor Vierhaus |
| 2010 | The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. | Zdenek Kotsek, Jaroslav Skarvada, Josef Strnadel |
| 2010 | On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable Platforms. | George Kornaros, Antonios Motakis |
| 2010 | Scalable Architecture for Wavelength-Switched Optical NoC with Multicasting Capability. | Somayyeh Koohi, Alireza Shafaei, Shaahin Hessabi |
| 2010 | Low Power FPGA Implementations of 256-bit Luffa Hash Function. | Paris Kitsos, Nicolas Sklavos, Athanassios N. Skodras |