| 2010 | QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration. | Dennis Bode, Mladen Berekovic, Axel Borkowski, Ludger Buker |
| 2010 | Design Methodology for a High Performance Robust DVB-S2 Decoder Implementation. | Florent Berthelot, Franois Charot, Charles Wagner, Christophe Wolinski |
| 2010 | New Digital Control Technique for Improving Transient Response in DC - DC Converters. | Majd Ghazi Batarseh, Ehab Shobaki, Xiang Fang, Haibing Hu, Issa Batarseh |
| 2010 | Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power Consumption. | Enrique Barajas, Diego Mateo, Jos Luis Gonzlez |
| 2010 | Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG. | Jiri Balcarek, Petr Fiser, Jan Schmidt |
| 2010 | Reconfigurable Fault-Tolerant System Sychronization. | Jan Balach, Ondrej Novk |
| 2010 | Area-Efficient Multi-moduli Squarers for RNS. | Dimitris Bakalis, Haridimos T. Vergos |
| 2010 | Automated Power Characterization for Run-Time Power Emulation of SoC Designs. | Christian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiss, Josef Haid |
| 2010 | H.264 Color Components Video Decoding Parallelization on Multi-core Processors. | Elias Baaklini, Hassan Sbeity, Smal Niar, Nouhad Amaneddine |
| 2010 | C?aSH: Structural Descriptions of Synchronous Hardware Using Haskell. | Christiaan Baaij, Matthijs Kooijman, Jan Kuper, Arjan Boeijink, Marco Gerards |
| 2010 | Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor. | Muhammad Waqar Azhar, Tung Thanh Hoang, Per Larsson-Edefors |
| 2010 | A Formal Condition to Stop an Incremental Automatic Functional Diagnosis. | Luca Amati, Cristiana Bolchini, Fabio Salice, Federico Franzoso |
| 2010 | Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications. | Levent Aksoy, Eduardo Costa, Paulo F. Flores, Jos Monteiro |
| 2010 | A Computation and Power Reduction Technique for H.264 Intra Prediction. | Yusuf Adibelli, Mustafa Parlak, Ilker Hamzaoglu |
| 2009 | A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction. | Amir Ehsani Zonouz, Mehrdad Seyrafi, Arghavan Asad, Mohsen Soryani, Mahmood Fathy, Reza Berangi |
| 2009 | Design of a Highly Dependable Beamforming Chip. | Xiao Zhang, Hans G. Kerkhoff |
| 2009 | Pipelining-Based High Throughput Low Energy Mapping on Network-on-Chip. | Ming-Yan Yu, Ming Li, Jun-Jie Song, Fang-Fa Fu, Yu-Xin Bai |
| 2009 | Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks. | Alexander Wei Yin, Liang Guang, Ethiopia Nigussie, Pasi Liljeberg, Jouni Isoaho, Hannu Tenhunen |
| 2009 | Architecture-Driven Synthesis of Reconfigurable Cells. | Christophe Wolinski, Krzysztof Kuchcinski, Erwan Raffin, Franois Charot |
| 2009 | Combined SD-RNS Constant Multiplication. | Evangelos Vassalos, Dimitris Bakalis |
| 2009 | Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm. | Fabrizio Vacca, Guido Masera, Hazem Moussa, Amer Baghdadi, Michel Jzquel |
| 2009 | Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems. | Raimund Ubar, Sergei Kostin, Jaan Raik |
| 2009 | On the Risk of Fault Coupling over the Chip Substrate. | Peter Tummeltshammer, Andreas Steininger |
| 2009 | Design, Simulation and Performance Evaluation of a NAND Based Single-electron 2-4 Decoder. | Thomas Tsiolakis, Nikos Konofaos, George Alexiou |
| 2009 | An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs. | Shadi Traboulsi, Michael Meitinger, Rainer Ohlendorf, Andreas Herkersdorf |