| 2005 | Message from the Program Chair. | |
| 2005 | Copyright. | |
| 2005 | Title Page. | |
| 2005 | Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction. | Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz, Petru Eles |
| 2005 | A Constraints Programming Approach for Fabric Cell Synthesis. | Christophe Wolinski, Krzysztof Kuchcinski |
| 2005 | Yield-aware Floorplanning. | Zhaojun Wo, Israel Koren, Maciej J. Ciesielski |
| 2005 | Efficient MLP Digital Implementation on FPGA. | Salvatore Vitabile, Vincenzo Conti, Fulvio Gennaro, Filippo Sorbello |
| 2005 | Capturing Processor Architectures from Protocol Processing Applications: a Case Study. | Seppo Virtanen, Jani Paakkulainen, Tero Nurmi |
| 2005 | Design of A Development Platform for HW/SW Codesign ofWireless Integrated Sensor Nodes. | Kashif Virk, Jan Madsen, Andreas Vad Lorentzen, Martin Leopold, Philippe Bonnet |
| 2005 | Embedded Object Architecture. | Tero Vallius, Juha Rning |
| 2005 | Exploring Graphics Processor Performance for General Purpose Applications. | Pedro Trancoso, Maria Charalambous |
| 2005 | Dynamic Split: Flexible Border Between Instruction and Data Cache. | Pedro Trancoso |
| 2005 | Wireless Sensor Systems - Constraints and Opportunities. | Dirk Timmermann |
| 2005 | Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. | Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz |
| 2005 | Predictable embedding of large data structures in multiprocessor networks-on-chip. | Sander Stuijk, Twan Basten, Bart Mesman, Marc Geilen |
| 2005 | Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. | Josef Strnadel, Zdenek Kotsek |
| 2005 | RF CMOS Circuits for Ad-Hoc Networks and Wearable Computing. | Chris Siu, Soraya Kasnavi, Kris Iniewski, Frederic Nabki |
| 2005 | Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs. | Miguel Lino Silva, Joo Canas Ferreira |
| 2005 | An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS. | Md. Sumon Shahriar, A. R. Mustafa, Chowdhury Farhan Ahmed, Abu Ahmed Ferdaus, A. N. M. Zaheduzzaman, Shahed Anwar, Hafiz Md. Hasan Babu |
| 2005 | On LUT Cascade Realizations of FIR Filters. | Tsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki |
| 2005 | An Effective Framework for Enabling the Reuse of External Soft IP. | Soujanna Sarkar, Subash Chandar G. |
| 2005 | Cost-effective VLSI Design of Non Linear Image Processing Filters. | Sergio Saponara, Michele Cassiano, Stefano Marsi, Riccardo Coen, Luca Fanucci |
| 2005 | Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms. | Hamid Safizadeh, Hamid Noori, Mehdi Sedighi, Ali Jahanian, Neda Zolfaghari |
| 2005 | VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC Codes. | Massimo Rovini, Nicola E. L'Insalata, Francesco Rossi, Luca Fanucci |
| 2005 | An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable Architectures. | Fredy Rivera, Milagros Fernndez, Nader Bagherzadeh |