| 2003 | A Communication Model Based on an n-Dimensional Torus Architecture Using Deadlock-Free Wormhole Routing. | Philip K. F. Hlzenspies, Erik Schepers, Wouter Bach, Mischa Jonker, Bart Sikkes, Gerard J. M. Smit, Paul J. M. Havinga |
| 2003 | Fast Heuristics for the Edge Coloring of Large Graphs. | Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler |
| 2003 | Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. | Vladimir Hahanov, Raimund Ubar, Stanley Hyduke |
| 2003 | Temperature Influence on Power Consumption and Time Delay. | Adam Golda, Andrzej Kos |
| 2003 | Understanding Video Pixel Processing Applications for Flexible Implementations. | Om Prakash Gangwal, Johan G. W. M. Janssen, Selliah Rathnam, Erwin B. Bellers, Marc Duranton |
| 2003 | FC-Min: A Fast Multi-Output Boolean Minimizer. | Petr Fiser, Jan Hlavicka, Hana Kubtov |
| 2003 | Modelling and Simulation of a Digital IC System Using SimulPet: Application to a Speech Coding Communication IC. | Raquel Fernndez-Ramos, Jorge Romero-Snchez, Francisco J. Ros-Gmez, Jos F. Martn-Canales |
| 2003 | A Methodology for Designing Communication Architectures for Multiprocessor SoCs. | Vclav Dvork, Vladimr Kutlek |
| 2003 | An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs. | Radoslaw Czarnecki, Stanislaw Deniziak, Krzysztof Sapiecha |
| 2003 | Distance-aware L2 Cache Organizations for Scalable Multiprocessor Systems. | Sung Woo Chung, Hyong-Shik Kim, Chu Shik Jhon |
| 2003 | A Fast Additive Normalization Method for Exponential Computation. | Chichyang Chen, Rui-Lin Chen, Ming-Hwa Sheu |
| 2003 | Compiler-Directed Management of Instruction Accesses. | Guilin Chen, Guangyu Chen, Ismail Kadayif, Wei Zhang, Mahmut T. Kandemir, Ibrahim Kolcu, Ugur Sezer |
| 2003 | RDSP: A RISC DSP based on Residue Number System. | Ricardo Chaves, Leonel Sousa |
| 2003 | Exact Numerical Processing. | Juan Manuel Garca Chamizo, Jernimo Mora Pascual, Higinio Mora Mora |
| 2003 | Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects. | Gregorio Cappuccino |
| 2003 | A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges. | Winthir Brunnbauer, Thomas Wild, Jrgen Foag, Nuria Pazos |
| 2003 | Eccentric SoC Architectures as the Future Norm. | Gordon J. Brebner |
| 2003 | HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming. | Karthikeyan Bhasyam, Kia Bazargan |
| 2003 | A methodology for the design of AHB bus master wrappers. | Marc Bertola, Guy Bois |
| 2003 | A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator. | Marco Bera, Giovanni Danese, Ivo De Lotto, Francesco Leporati, Alvaro Spelgatti |
| 2003 | A Real Time, Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image Applications. | Oguz Benderli, Yusuf agatay Tekmen, A. Neslin Ismailoglu |
| 2003 | Back-End Dynamic Resource Allocation Heuristics for Power-Aware High-Performance Clustered Architectures. | Amirali Baniasadi |
| 2003 | Reversible Logic Synthesis for Minimization of Full-Adder Circuit. | Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury |
| 2003 | Power/Area Analysis and Optimization of a DS-SS receiver for an Integrated Sensor Microsystem. | Nizamettin Aydin, Tughrul Arslan, David R. S. Cumming |
| 2003 | A VLIW Architecture for Logarithmic Arithmetic. | Mark G. Arnold |