| 2021 | FPGA Hardware Acceleration Framework for Anomaly-based Intrusion Detection System in IoT. | Duc-Minh Ngo, Andriy Temko, Colin C. Murphy, Emanuel M. Popovici |
| 2021 | HALF: Holistic Auto Machine Learning for FPGAs. | Jonas Ney, Dominik Marek Loroch, Vladimir Rybalkin, Nico Weber, Jens Krger, Norbert Wehn |
| 2021 | FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access. | Jian Meng, Shreyas Kolala Venkataramanaiah, Chuteng Zhou, Patrick Hansen, Paul N. Whatmough, Jae-sun Seo |
| 2021 | Minimal Overhead Optical Time-Domain Reflectometer Via I/O Integrated Data Converter Enabled by Field Programmable Voltage Offset. | Thomas Mauldin, Zhenyu Xu, Tao Wei |
| 2021 | DO-GPU: Domain Optimizable Soft GPUs. | Rui Ma, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, Rajesh Vivekanandham, Aravind Dasu, Martin Langhammer, Derek Chiou |
| 2021 | Leveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array Architectures. | Linqiao Liu, Stephen Brown |
| 2021 | Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators. | Vasileios Leon, Kiamal Z. Pekmestzi, Dimitrios Soudris |
| 2021 | Dense FPGA Compute Using Signed Byte Tuples. | Martin Langhammer, Simon Finn, Sergey Gribok, Bogdan Pasca |
| 2021 | Communication-avoiding micro-architecture to compute Xcorr scores for peptide identification. | Sumesh Kumar, Fahad Saeed |
| 2021 | A comparison of real-time 4K/UltraHD connected component labelling architectures. | Marcin Kowalczyk, Tomasz Kryjak |
| 2021 | HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem. | Vatistas Kostalabros, Jordi Ribes-Gonzlez, Oriol Farrs, Miquel Moret, Carles Hernndez |
| 2021 | FPGA acceleration in EVOLVE's Converged Cloud-HPC Infrastructure. | Konstantina Koliogeorgi, Fekhr Eddine Keddous, Dimosthenis Masouros, Antony Chazapis, Michelle Aubrun, Sotirios Xydis, Angelos Bilas, Romain Hugues, Jean-Thomas Acquaviva, Huy-Nam Nguyen, Dimitrios Soudris |
| 2021 | A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms. | Alexander Klemd, Bernd Klauer, Johannes Timmermann, Delf Sachau |
| 2021 | Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation. | Jin Hee Kim, Jason Helge Anderson |
| 2021 | Optimizing Deep Learning Decoders for FPGA Implementation. | Emmanouil Kavvousanos, Vassilis Paliouras |
| 2021 | HiPReP: High-Performance Reconfigurable Processor - Architecture and Compiler. | Philipp S. Ksgen, Mohamed Messelka, Markus Weinhardt |
| 2021 | Design For Agility: A Modular Reconfigurable Platform for Heterogeneous Many-Core Architectures. | Ahmed Kamaleldin, Diana Ghringer |
| 2021 | Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration. | Hasan Irmak, Daniel Ziener, Nikolaos Alachiotis |
| 2021 | Towards the Efficient Multi-Platform Execution of Deep Neural Networks. | Hector Gerardo Muoz Hernandez |
| 2021 | EasyNet: 100 Gbps Network for HLS. | Zhenhao He, Dario Korolija, Gustavo Alonso |
| 2021 | Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. | Christian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig, Jrgen Teich |
| 2021 | An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising. | Nobuho Hashimoto, Shinya Takamaeda-Yamazaki |
| 2021 | An Emulation of Quantum Error-Correction on an FPGA device. | Michael Hart, John McAllister, Leo Rogers, Charles Gillan |
| 2021 | RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education. | Sarah L. Harris, Daniel Chaver, Luis Piuel, Jos Ignacio Gmez Prez, M. Hamza Liaqat, Zubair L. Kakakhel, Olof Kindgren, Robert Owen |
| 2021 | An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment. | Abbas Haghi, Santiago Marco-Sola, Lluc Alvarez, Dionysios Diamantopoulos, Christoph Hagleitner, Miquel Moret |