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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2012Multi-kernel floorplanning for enhanced CGRAS.Aaron Wood, Adam Knight, Benjamin Ylvisaker, Scott Hauck
2012Design space exploration for automatically generated cryptographic hardware using functional languages.Davy Wolfs, Kris Aerts, Nele Mentens
2012A two step hardware design method using CλaSH.Rinse Wester, Christiaan Baaij, Jan Kuper
2012CaaS: Core as a service realizing hardware sercices on reconfigurable MPSoCS.Chao Wang, Xi Li, Junneng Zhang, Peng Chen, Xuehai Zhou
2012Examination of the concept of a row-column separated median filter.Di Wang, Christopher T. Clarke, A. N. Evans
2012A framework for Open Tiled Manycore System-On-Chip.Stefan Wallentowitz, Andreas Lankes, Aurang Zaib, Thomas Wild, Andreas Herkersdorf
2012Sliding block Viterbi decoders in FPGA.Mrio P. Vstias, Horcio C. Neto, Helena Sarmento
2012Maximizing the reuse of routing resources in a reconfiguration-aware connection router.Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt
2012Modeling of dynamic reconfigurable systems with Haskell.Bahram N. Uchevler, Kjetil Svarstad
2012An FPGA acceleration of a level set segmentation method.Haruhisa Tsuyama, Tsutomu Maruyama
2012A region merging approach for image segmentation on FPGA.Dang Ba Khac Trieu, Tsutomu Maruyama
2012An energy-efficient hardware accelerator for Robust Header Compression in LTE-Advanced terminals.Shadi Traboulsi, Wenlong Zhang, David Szczesny, Anas Showk, Attila Bilgic
2012Data coding functions for Software Defined Radios implemented on R3TOS.Raul Torrego, Inaki Val, Eaut Muxika, Xabier Iturbe, Khaled Benkrid
2012Verification of streaming designs by combining symbolic simulation and equivalence checking.Tim Todman, Wayne Luk
2012Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.Kazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka, Masami Urano
2012Intra-chip physical parameter sensor for FPGAS using flip-flop metastability.Ghaith Tarawneh, Terrence S. T. Mak, Alex Yakovlev
2012A scalable complex event processing framework for combination of SQL-based continuous queries and C/C++ functions.Takashi Takenaka, Masamichi Takagi, Hiroaki Inoue
2012Dynamic query switching for complex event processing on FPGAs.Masamichi Takagi, Takashi Takenaka, Hiroaki Inoue
2012Improving memory support in the VTR flow.Andrew Somerville, Kenneth B. Kent
2012Dataflow graph partitioning for high level synthesis.Sharad Sinha, Thambipillai Srikanthan
2012Power/performance optimization in FPGA-based asymmetric multi-core systems.Bruno de Abreu Silva, Vanderlei Bonato
2012Automatic generation of application-specific accelerators for FPGAs from python loop nests.David Sheffield, Michael J. Anderson, Kurt Keutzer
2012On the difficulty of pin-to-wire routing in FPGAs.Niyati Shah, Jonathan Rose
2012Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism.Junichi Sawada, Hiroaki Nishi
2012Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration.Rubn Salvador, Andrs Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Luks Sekanina
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