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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2024Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs.Shivam Aggarwal, Hans Jakob Damsgaard, Alessandro Pappalardo, Giuseppe Franco, Thomas B. Preuer, Michaela Blott, Tulika Mitra
2023Bayesian Optimization for Efficient Heterogeneous MPSoC Based DNN Accelerator Runtime Tuning.Xuqi Zhu, Cong Gao, Sangeet Saha, Xiaojun Zhai, Klaus D. McDonald-Maier
2023GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors.Guanglei Zhou, Mirjana Stojilovic, Jason Helge Anderson
2023FPL Demo: A Learning-Based Motion Artefact Detector for Heterogeneous Platforms.Yunyi Zhao, Yunjia Xia, Rui C. V. Loureiro, Hubin Zhao, Uwe Dolinsky, Shufan Yang
2023Token Packing for Transformers with Variable-Length Inputs.Tiandong Zhao, Siyuan Miao, Shaoqiang Lu, Jialin Cao, Jun Qiu, Xiao Shi, Kun Wang, Lei He
2023A Novel Hardware Accelerator of NeRF Based on Xilinx UltraScale and UltraScale+ FPGA.Baoze Zhao, Wenjin Huang, Yihua Huang
2023Building a Reusable and Extensible Automatic Compiler Infrastructure for Reconfigurable Devices.Zhenya Zang, Uwe Dolinsky, Pietro Ghiglio, Stefano Cherubin, Mehdi Goli, Shufan Yang
2023FSSD: FPGA-Based Emulator for SSDs.Luyang Yu, Yizhen Lu, Meghna Mandava, Edward Richter, Vikram Sharma Mailthody, Seungwon Min, Wen-Mei W. Hwu, Deming Chen
2023Mixed-TD: Efficient Neural Network Accelerator with Layer-Specific Tensor Decomposition.Zhewen Yu, Christos-Savvas Bouganis
2023FPGA Acceleration of Rotation in Homomorphic Encryption Using Dynamic Data Layout.Yang Yang, Weihang Long, Rajgopal Kannan, Viktor K. Prasanna
2023Exploring FPGA Acceleration for Distributed Serverless Computing.Ziyi Yang, Suhaib A. Fahmy
2023fpgaHART: A Toolflow for Throughput-Oriented Acceleration of 3D CNNs for HAR onto FPGAs.Petros Toupas, Christos-Savvas Bouganis, Dimitrios Tzovaras
2023Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis.Robert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede
2023Optimization Techniques for Hestenes-Jacobi SVD on FPGAs.Lukas Stasytis, Zsolt Istvn
2023Preface.Ioannis Sourdis, Nele Mentens, Leonel Sousa, Pedro Trancoso
2023MSDF-SGD: Most-Significant Digit-First Stochastic Gradient Descent for Arbitrary-Precision Training.Changjun Song, Yongming Tang, Jiyuan Liu, Sige Bian, Danni Deng, He Li
2023FABulous Demo: Open Source FPGA on Sky130.Myrtle Shah, Jakob Ternes, Dirk Koch
2023Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs.Gabriel Rodriguez-Canal, Nick Brown, Tim Dykes, Jessica R. Jones, Utz-Uwe Haus
2023MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration.Zhiqiang Que, Shuo Liu, Markus Rognlien, Ce Guo, Jos Gabriel F. Coutinho, Wayne Luk
2023Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based Approach.Jos Oliver, Carlos lvarez, Teresa Cervero, Xavier Martorell, John D. Davis, Eduard Ayguad
2023HashCache: High-Performance State Tracking for Resilient FPGA-Based Packet Processing.Michael Offel, Andreas Ley, Sven Hager
2023A Novel Strategy for Flexible Placement and Routing of AVS Sensors on FPGAs.Christoph Niemann, Michael Rethfeldt, Dirk Timmermann
2023SPADES: A Productive Design Flow for Versal Programmable Logic.Tan Nguyen, Zachary Blair, Stephen Neuendorffer, John Wawrzynek
2023Automated Masking of FPGA-Mapped Designs.Nicolai Mller, Sergej Meschkov, Dennis R. E. Gnad, Mehdi B. Tahoori, Amir Moradi
2023PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN Acceleration.Alexander Montgomerie-Corcoran, Zhewen Yu, Jianyi Cheng, Christos-Savvas Bouganis
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