| 2006 | High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA Architectures. | Rafael A. Arce-Nazario, Manuel Jimnez, Domingo Rodrguez |
| 2006 | Dynamic Memory Sub-System for Reconfigurable Platforms. | Su-Shin Ang, George A. Constantinides |
| 2006 | Fast Emulation of Permanent Faults in VLSI Systems. | David de Andrs, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil |
| 2006 | A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors. | Hideharu Amano, Yohei Hasegawa, Shohei Abe, Kenichiro Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, Takuro Nakamura, Takashi Nishimura |
| 2006 | Detection Module in a Complementary Set of Sequences-Based Pulse Compression System. | Fernando J. lvarez, lvaro Hernndez, Jess Urea, Juan Jess Garca, Ana Jimnez, P. Santa Teresa |
| 2006 | Tutorial: 65 NM FPGAs, A Look Under the Hood Technology, Features, and Applications. | Peter Alfke |
| 2006 | A Reconfigurable Viterbi Decoder for a Communication Platform. | Imran Ahmed, Tughrul Arslan |
| 2006 | FPGA Based Architectures for H. 264/AVC Video Compression Standard. | Luciano Volcan Agostini, Sergio Bampi |
| 2006 | FPGA Design of A H.264/AVC Main Profile Decoder for HDTV. | Luciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana Gadelha Serra dos Santos, Sergio Bampi, Altamiro Amadeu Susin |
| 2005 | Communication Synthesis in a multiprocessor environment. | Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere |
| 2005 | A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata. | Peter Zipf, Oliver Soffke, Andre Schumacher, Clemens Schlachta, Radu Dogaru, Manfred Glesner |
| 2005 | Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata. | Peter Zipf, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred Glesner |
| 2005 | Ziggurat-based Hardware Gaussian Random Number Generator. | Guanglie Zhang, Philip Heng Wai Leong, Dong-U Lee, John D. Villasenor, Ray C. C. Cheung, Wayne Luk |
| 2005 | NetFlow Probe Intended for High-Speed Networks. | Martin Zdnk, Tomas Pecenka, Jan Korenek |
| 2005 | Bitwise Optimised CAM for Network Intrusion Detection Systems. | Sherif Yusuf, Wayne Luk |
| 2005 | Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement. | Anthony J. Yu, Guy G. Lemieux |
| 2005 | A 11 GHz FPGA with Test Applications. | Chao You, Jong-Ru Guo, Michael Chu, Russell P. Kraft, Bryan S. Goda, John F. McDonald |
| 2005 | Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks. | Andy Gean Ye, Jonathan Rose |
| 2005 | A High Performance Hardware Architecture for an SAD Reuse based Hierarchical Motion Estimation Algorithm for H.264 Video Coding. | Sinan Yalcin, Hasan F. Ates, Ilker Hamzaoglu |
| 2005 | QPF: Efficient Quadratic Placement for FPGAs. | Yonghong Xu, Mohammed A. S. Khalid |
| 2005 | Towards a Reconfigurable Tracking System. | Sebastien C. Wong, Mark Jasiunas, David A. Kearney |
| 2005 | Energy-Efficient NoC for Best-Effort Communication. | Pascal T. Wolkotte, Gerard J. M. Smit, Jens E. Becker |
| 2005 | An FPGA Network Architecture for Accelerating 3DES - CBC. | Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann |
| 2005 | Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor. | Chi-Wei Wang, Nicholas P. Carter, Richard B. Kujoth, Jeffrey J. Cook, Derek B. Gottlieb |
| 2005 | Highly Automated FPGA Synthesis of Application-Specific Protocol Processors. | Seppo Virtanen, Dragos Truscan, Jani Paakkulainen, Jouni Isoaho, Johan Lilius |