| 2009 | Improved heuristics for finite word-length polynomial datapath optimization. | Bijan Alizadeh, Masahiro Fujita |
| 2009 | Characterizing within-die variation from multiple supply port IDDQ measurements. | Kanak Agarwal, Dhruva Acharyya, Jim Plusquellic |
| 2008 | Statistical path selection for at-speed test. | Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chandu Visweswariah |
| 2008 | Advancing supercomputer performance through interconnection topology synthesis. | Yi Zhu, Michael B. Taylor, Scott B. Baden, Chung-Kuan Cheng |
| 2008 | A highly efficient optimization algorithm for pixel manipulation in inverse lithography technique. | Jinyu Zhang, Wei Xiong, Yan Wang, Zhiping Yu, Min-Chun Tsai |
| 2008 | FastRoute3.0: a fast and high quality global router based on virtual capacity. | Yanheng Zhang, Yue Xu, Chris Chu |
| 2008 | System-level thermal aware design of applications with uncertain execution time. | Sushu Zhang, Karam S. Chatha |
| 2008 | Yield-aware hierarchical optimization of large analog integrated circuits. | Guo Yu, Peng Li |
| 2008 | Sparse implicit projection (SIP) for reduction of general many-terminal networks. | Zuochang Ye, Dmitry Vasilyev, Zhenhai Zhu, Joel R. Phillips |
| 2008 | SPM management using Markov chain based data access prediction. | Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kandemir, Ozcan Ozturk |
| 2008 | Integrated code and data placement in two-dimensional mesh based chip multiprocessors. | Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kandemir, Mustafa Karaky, Mary Jane Irwin |
| 2008 | MAPS: multi-algorithm parallel circuit simulation. | Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif |
| 2008 | BSG-Route: a length-matching router for general topology. | Tan Yan, Martin D. F. Wong |
| 2008 | Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method. | Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Lifeng Wu |
| 2008 | Verifying external interrupts of embedded microprocessor in SoC with on-chip bus. | Fu-Ching Yang, Jing-Kun Zhong, Ing-Jer Huang |
| 2008 | Overlay aware interconnect and timing variation modeling for double patterning technology. | Jae-Seok Yang, David Z. Pan |
| 2008 | Accurate energy breakeven time estimation for run-time power gating. | Hao Xu, Wen-Ben Jone, Ranga Vemuri |
| 2008 | Design and optimization of a digital microfluidic biochip for protein crystallization. | Tao Xu, Krishnendu Chakrabarty, Vamsee K. Pamula |
| 2008 | Adjustment-based modeling for statistical static timing analysis with high dimension of variability. | Lin Xie, Azadeh Davoodi, Jun Zhang, Tai-Hsuan Wu |
| 2008 | PaRS: fast and near-optimal grid-based cell sizing for library-based design. | Tai-Hsuan Wu, Azadeh Davoodi |
| 2008 | Linear constraint graph for floorplan optimization with soft blocks. | Jia Wang, Hai Zhou |
| 2008 | Path-RO: a novel on-chip critical path delay measurement under process variations. | Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta |
| 2008 | Linear analysis of random process variability. | Victoria Wang, Dejan Markovic |
| 2008 | Embedded software verification: challenges and solutions. | Chao Wang, Malay K. Ganai, Shuvendu K. Lahiri, Daniel Kroening |
| 2008 | Guiding global placement with wire density. | Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan |