| 2007 | Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip. | Zhonghai Lu, Axel Jantsch |
| 2007 | Mapping model with inter-array memory sharing for multidimensional signal processing. | Ilie I. Luican, Hongwei Zhu, Florin Balasa |
| 2007 | A self-adjusting clock tree architecture to cope with temperature variations. | Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail |
| 2007 | An efficient method for statistical circuit simulation. | Frank Liu |
| 2007 | Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization. | Xin Li, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi |
| 2007 | Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction. | Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Li, Yao-Wen Chang |
| 2007 | Device and architecture concurrent optimization for FPGA transient soft error rate. | Yan Lin, Lei He |
| 2007 | A selective pattern-compression scheme for power and test-data reduction. | Chia-Yi Lin, Hung-Ming Chen |
| 2007 | An efficient algorithm for statistical circuit optimization using Lagrangian relaxation. | I-Jye Lin, Yao-Wen Chang |
| 2007 | A fast band-matching technique for interconnect inductance modeling. | Hong Li, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan |
| 2007 | Using functional independence conditions to optimize the performance of latency-insensitive systems. | Cheng-Hong Li, Luca P. Carloni |
| 2007 | Parameterized model order reduction via a two-directional Arnoldi process. | Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng |
| 2007 | Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques. | Xiaoyao Liang, Kerem Turgay, David M. Brooks |
| 2007 | An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. | Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang |
| 2007 | Scalable exploration of functional dependency by interpolation and incremental SAT solving. | Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko |
| 2007 | Engineering change using spare cells with constant insertion. | Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska |
| 2007 | Automated refinement checking of concurrent systems. | Sudipta Kundu, Sorin Lerner, Rajesh Gupta |
| 2007 | Formal verification at higher levels of abstraction. | Daniel Kroening, Sanjit A. Seshia |
| 2007 | Enhancing design robustness with reliability-aware resynthesis and logic simulation. | Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes |
| 2007 | Optimal bus sequencing for escape routing in dense PCBs. | Hui Kong, Tan Yan, Martin D. F. Wong, Muhammet Mustafa Ozdal |
| 2007 | Stimulus generation for constrained random simulation. | Nathan Kitchen, Andreas Kuehlmann |
| 2007 | Minimizing leakage power in sequential circuits by using mixed | Jaehyun Kim, Youngsoo Shin |
| 2007 | Equalized interconnects for on-chip networks: modeling and optimization framework. | Byungsub Kim, Vladimir Stojanovic |
| 2007 | Compatibility path based binding algorithm for interconnect reduction in high level synthesis. | Taemin Kim, Xun Liu |
| 2007 | Device-circuit co-optimization for mixed-mode circuit design via geometric programming. | Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong Ken Yang |