| 2007 | Variable domain transformation for linear PAC analysis of mixed-signal systems. | Jaeha Kim, Kevin D. Jones, Mark A. Horowitz |
| 2007 | Monte-Carlo driven stochastic optimization framework for handling fabrication variability. | Vishal Khandelwal, Ankur Srivastava |
| 2007 | A nonlinear cell macromodel for digital applications. | Chandramouli V. Kashyap, Chirayu S. Amin, Noel Menezes, Eli Chiprout |
| 2007 | Increasing data-bandwidth to instruction-set extensions through register clustering. | Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
| 2007 | Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering. | Georgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy, Chaitali Chakrabarti |
| 2007 | Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance. | Kunhyuk Kang, Sang Phill Park, Kaushik Roy, Muhammad Ashraful Alam |
| 2007 | Data locality enhancement for CMPs. | Mahmut T. Kandemir |
| 2007 | Estimation of delay test quality and its application to test generation. | Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo |
| 2007 | Exploiting STI stress for performance. | Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu |
| 2007 | Timing variation-aware high-level synthesis. | Jongyoon Jung, Taewhan Kim |
| 2007 | Soft-edge flip-flops for improved timing yield: design and optimization. | Vivek Joshi, David T. Blaauw, Dennis Sylvester |
| 2007 | Inductive equivalence checking under retiming and resynthesis. | Jie-Hong Roland Jiang, Wei-Lun Hung |
| 2007 | Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. | M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli |
| 2007 | Variation-aware performance verification using at-speed structural test and statistical timing. | Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah |
| 2007 | Efficient path delay test generation based on stuck-at test generation using checker circuitry. | Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara |
| 2007 | Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping. | Yu Hu, Victor Shih, Rupak Majumdar, Lei He |
| 2007 | Unified adaptivity optimization of clock and logic signals. | Shiyan Hu, Jiang Hu |
| 2007 | Multi-layer interconnect performance corners for variation-aware timing analysis. | Frank Huebbers, Ali Dasdan, Yehea I. Ismail |
| 2007 | Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates. | Yu Hu, Satyaki Das, Steven Trimberger, Lei He |
| 2007 | Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors. | Sivaram Gopalakrishnan, Priyank Kalla, M. Brandon Meredith, Florian Enescu |
| 2007 | Incremental component implementation selection: enabling ECO in compositional system synthesis. | Soheil Ghiasi |
| 2007 | A fast and high-capacity electromagnetic solution for highspeed IC design. | Houle Gan, Dan Jiao |
| 2007 | Victim alignment in crosstalk aware timing analysis. | Ravikishore Gandikota, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada |
| 2007 | A novel technique for incremental analysis of on-chip power distribution networks. | Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao |
| 2007 | A geometric approach for early power grid verification using current constraints. | Imad A. Ferzli, Farid N. Najm, Lars Kruse |