| 2007 | Strategies for improving the parametric yield and profits of 3D ICs. | Cesare Ferri, Sherief Reda, R. Iris Bahar |
| 2007 | A methodology for timing model characterization for statistical static timing analysis. | Zhuo Feng, Peng Li |
| 2007 | Run-time adaptive on-chip communication scheme. | Mohammad Abdullah Al Faruque, Thomas Ebi, Jrg Henkel |
| 2007 | CacheCompress: a novel approach for test data compression with cache for IP embedded cores. | Hao Fang, Chenguang Tong, Bo Yao, Xiaodi Song, Xu Cheng |
| 2007 | Efficient VCO phase macromodel generation considering statistical parametric variations. | Wei Dong, Zhuo Feng, Peng Li |
| 2007 | Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture. | Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei Wang |
| 2007 | Temperature aware microprocessor floorplanning considering application dependent power load. | Chunta Chu, Xinyi Zhang, Lei He, Tong Jing |
| 2007 | BoxRouter 2.0: architecture and implementation of a hybrid and robust global router. | Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan |
| 2007 | The effect of process variation on device temperature in FinFET circuits. | Jung Hwan Choi, Jayathi Murthy, Kaushik Roy |
| 2007 | The FAST methodology for high-speed SoC/computer simulation. | Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Zheng Xu |
| 2007 | Timing budgeting under arbitrary process variations. | Ruiming Chen, Hai Zhou |
| 2007 | Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems. | Jian-Jia Chen, Tei-Wei Kuo |
| 2007 | An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon. | Yu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-Chieh Chang |
| 2007 | Skew aware polarity assignment in clock tree. | Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang |
| 2007 | Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. | Lei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig |
| 2007 | ECO timing optimization using spare cells. | Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang |
| 2007 | Novel wire density driven full-chip routing for CMP variation control. | Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang |
| 2007 | Yield-driven near-threshold SRAM design. | Gregory K. Chen, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim |
| 2007 | A design flow dedicated to multi-mode architectures for DSP applications. | Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin |
| 2007 | A hybrid scheme for compacting test responses with unknown values. | Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei |
| 2007 | Automating post-silicon debugging and repair. | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
| 2007 | MOSFET modeling for 45nm and beyond. | Yu Cao, Colin C. McAndrew |
| 2007 | A general model for performance optimization of sequential systems. | Dmitry Bufistov, Jordi Cortadella, Michael Kishinevsky, Sachin S. Sapatnekar |
| 2007 | Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. | Philip Brisk, Ajay Kumar Verma, Paolo Ienne |
| 2007 | Stabilizing schemes for piecewise-linear reduced order models via projection and weighting functions. | Bradley N. Bond, Luca Daniel |