| 2006 | Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. | Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez |
| 2006 | Improvements to combinational equivalence checking. | Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas En |
| 2006 | PPV-HB: harmonic balance for oscillator/PLL phase macromodels. | Ting Mei, Jaijeet S. Roychowdhury |
| 2006 | Automation in mixed-signal design: challenges and solutions in the wake of the nano era. | Trent McConaghy, Georges G. E. Gielen |
| 2006 | System-level process-driven variability analysis for single and multiple voltage-frequency island systems. | Diana Marculescu, Siddharth Garg |
| 2006 | Automatic memory reductions for RTL model verification. | Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon |
| 2006 | Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization. | Murari Mani, Ashish Kumar Singh, Michael Orshansky |
| 2006 | Organic electronic device modeling at the nanoscale. | Conor F. Madigan, Vladimir Bulovic |
| 2006 | Formal model of data reuse analysis for hierarchical memory organizations. | Ilie I. Luican, Hongwei Zhu, Florin Balasa |
| 2006 | Exploring linear structures of critical path delay faults to reduce test efforts. | Shun-Yen Lu, Pei-Ying Hsieh, Jing-Jia Liou |
| 2006 | Current path analysis for electrostatic discharge protection. | Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Wei-Ting Tu, Chih-Hung Liu, Yao-Wen Chang, Sy-Yen Kuo |
| 2006 | Verification of analog/mixed-signal circuits using labeled hybrid petri nets. | Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda |
| 2006 | A revisit to floorplan optimization by Lagrangian relaxation. | Chuan Lin, Hai Zhou, Chris C. N. Chu |
| 2006 | An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management. | Sheng-Chih Lin, Kaustav Banerjee |
| 2006 | Stable and compact inductance modeling of 3-D interconnect structures. | Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh |
| 2006 | Microarchitecture parameter selection to optimize system performance under process variation. | Xiaoyao Liang, David M. Brooks |
| 2006 | Post-routing redundant via insertion and line end extension with via density consideration. | Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao |
| 2006 | On bounding the delay of a critical path. | Leonard Lee, Li-C. Wang |
| 2006 | Voltage island aware floorplanning for power and timing optimization. | Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang |
| 2006 | TP-PPV: piecewise nonlinear, time-shifted oscillator macromodel extraction for fast, accurate PLL simulation. | Xiaolue Lai, Jaijeet S. Roychowdhury |
| 2006 | Near-term industrial perspective of analog CAD. | Christopher Labrecque |
| 2006 | A spectrally accurate integral equation solver for molecular surface electrostatics. | Shih-Hsien Kuo, Jacob White |
| 2006 | Efficient Boolean characteristic function for fast timed ATPG. | Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang |
| 2006 | An analytical model for negative bias temperature instability. | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
| 2006 | A statistical framework for post-silicon tuning through body bias clustering. | Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw |