| 2006 | Information processing in nanoscale arrays: DNA assembly, molecular devices, nano-array architectures. | Richard A. Kiehl |
| 2006 | Fill for shallow trench isolation CMP. | Andrew B. Kahng, Puneet Sharma, Alexander Zelikovsky |
| 2006 | Performance analysis of concurrent systems with early evaluation. | Jorge Jlvez, Jordi Cortadella, Michael Kishinevsky |
| 2006 | Studying a GALS FPGA architecture using a parameterized automatic design flow. | Xin Jia, Ranga Vemuri |
| 2006 | A new RLC buffer insertion algorithm. | Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi |
| 2006 | An optimal simultaneous diode/jumper insertion algorithm for antenna fixing. | Zhe-Wei Jiang, Yao-Wen Chang |
| 2006 | Network coding for routability improvement in VLSI. | Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson |
| 2006 | Trunk decomposition based global routing optimization. | Devang Jariwala, John Lillis |
| 2006 | Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts. | Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, Chuanjin Richard Shi |
| 2006 | An efficient technique for synthesis and optimization of polynomials in GF(2 | Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew |
| 2006 | Verification through the principle of least astonishment. | Beth Isaksen, Valeria Bertacco |
| 2006 | Guaranteeing performance yield in high-level synthesis. | Wei-Lun Hung, Xiaoxia Wu, Yuan Xie |
| 2006 | State re-encoding for peak current minimization. | Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh |
| 2006 | Timing-driven placement for heterogeneous field programmable gate array. | Bo Hu |
| 2006 | Runtime distribution-aware dynamic voltage scaling. | Sungpack Hong, Sungjoo Yoo, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo |
| 2006 | Loop pipelining for high-throughput stream computation using self-timed rings. | Gennette Gill, John Hansen, Montek Singh |
| 2006 | A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. | Swaroop Ghosh, Swarup Bhunia, Kaushik Roy |
| 2006 | Handling inductance in early power grid verification. | Nahi H. Abdul Ghani, Farid N. Najm |
| 2006 | Accelerating high-level bounded model checking. | Malay K. Ganai, Aarti Gupta |
| 2006 | Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search. | Zhaohui Fu, Sharad Malik |
| 2006 | Design and CAD challenges in 45nm CMOS and beyond. | David J. Frank, Ruchir Puri, Dorel Toma |
| 2006 | Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression. | Zhuo Feng, Peng Li |
| 2006 | Yield prediction for 3D capacitive interconnections. | Alberto Fazzi, Luca Magagni, Mario de Dominicis, Paolo Zoffoli, Roberto Canegallo, Pier Luigi Rolandi, Alberto L. Sangiovanni-Vincentelli, Roberto Guerrieri |
| 2006 | Precise identification of the worst-case voltage drop conditions in power grid verification. | Nestoras E. Evmorfopoulos, Dimitris P. Karampatzakis, Georgios I. Stamoulis |
| 2006 | A network-flow approach to timing-driven incremental placement for ASICs. | Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar |