| 2005 | Clustering for processing rate optimization. | Chuan Lin, Jia Wang, Hai Zhou |
| 2005 | Flip-flop insertion with shifted-phase clocks for FPGA power reduction. | Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck Chang |
| 2005 | Projection-based performance modeling for inter/intra-die variations. | Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J. Strojwas |
| 2005 | Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations. | Xin Li, Peng Li, Lawrence T. Pileggi |
| 2005 | Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations. | Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi |
| 2005 | Synthesis methodology for built-in at-speed testing. | Yinghua Li, Alex Kondratyev, Robert K. Brayton |
| 2005 | Improving scratch-pad memory reliability through compiler-guided data block duplication. | Feihui Li, Guilin Chen, Mahmut T. Kandemir, Ibrahim Kolcu |
| 2005 | Compiler-directed voltage scaling on communication links for reducing power consumption. | Feihui Li, Guilin Chen, Mahmut T. Kandemir |
| 2005 | Variational analysis of large power grids by exploring statistical sampling sharing and spatial locality. | Peng Li |
| 2005 | SPIDER: simultaneous post-layout IR-drop and metal density enhancement with redundant fill. | Kwok-Shing Leung |
| 2005 | Statistical based link insertion for robust clock network design. | Wai-Ching Douglas Lam, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen |
| 2005 | Incremental partitioning-based vectorless power grid verification. | Dionysios Kouroussis, Imad A. Ferzli, Farid N. Najm |
| 2005 | Embedded tutorial: formal equivalence checking between system-level models and RTL. | Alfred Klbl, Yuan Lu, Anmol Mathur |
| 2005 | FinFETs for nanoscale CMOS digital integrated circuits. | Tsu-Jae King |
| 2005 | The feasibility of on-chip interconnection using antennas. | Kenneth K. O, Kihong Kim, Brian A. Floyd, Jesal Mehta, Hyun Yoon, Chih-Ming Hung, Daniel F. Bravo, Timothy O. Dickson, Xiaoling Guo, Ran Li, Narasimhan Trichy, James Caserta, Wayne R. Bomstad II, Jason Branch, Dong-Jun Yang, Jose L. Bohorquez, Jie Chen, Eunyoung Seok, Li Gao, Aravind Sugavanam, Jau-Jr Lin, S. Yu, Changhua Cao, M.-H. Hwang, Y.-R. Ding, S.-H. Hwang, Hsin-Ta Wu, N. Zhang, Joe E. Brewer |
| 2005 | 2D data locality: definition, abstraction, and application. | Mahmut T. Kandemir |
| 2005 | Architecture and details of a high quality, large-scale analytical placer. | Andrew B. Kahng, Sherief Reda, Qinke Wang |
| 2005 | Intrinsic shortest path length: a new, accurate a priori wirelength estimator. | Andrew B. Kahng, Sherief Reda |
| 2005 | Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. | Rong Jiang, Wenyin Fu, Janet Meiling Wang, Vince Lin, Charlie Chung-Ping Chen |
| 2005 | Accurate delay computation for noisy waveform shapes. | Amit Jain, David T. Blaauw, Vladimir Zolotov |
| 2005 | A cache-defect-aware code placement algorithm for improving the performance of processors. | Tohru Ishihara, Farzan Fallah |
| 2005 | Fast-yet-accurate PVT simulation by combined direct and iterative methods. | Bo Hu, Chuanjin Richard Shi |
| 2005 | Statistical timing analysis with two-sided constraints. | Khaled R. Heloue, Farid N. Najm |
| 2005 | Wirelength optimization by optimal block orientation. | Xin Hao, Forrest Brewer |
| 2005 | Gate sizing using incremental parameterized statistical timing analysis. | Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov |