| 2004 | Cost-effective radiation hardening technique for combinational logic. | Quming Zhou, Kartik Mohanram |
| 2004 | Power estimation for cycle-accurate functional descriptions of hardware. | Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2004 | A soft error rate analysis (SERA) methodology. | Ming Zhang, Naresh R. Shanbhag |
| 2004 | Incremental deductive & inductive reasoning for SAT-based bounded model checking. | Liang Zhang, Mukul R. Prasad, Michael S. Hsiao |
| 2004 | Temporal floorplanning using the T-tree formulation. | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang |
| 2004 | Dynamic range estimation for nonlinear systems. | Bin Wu, Jianwen Zhu, Farid N. Najm |
| 2004 | Soft self-synchronising codes for self-calibrating communication. | Frederic Worm, Paolo Ienne, Patrick Thiran |
| 2004 | Wire-length prediction using statistical techniques. | Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak |
| 2004 | On per-test fault diagnosis using the X-fault model. | Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita |
| 2004 | Stochastic analysis of interconnect performance in the presence of process variations. | Janet Meiling Wang, Praveen Ghanta, Sarma B. K. Vrudhula |
| 2004 | Engineering details of a stable force-directed placer. | Kristofer Vorwerk, Andrew A. Kennings, Anthony Vannelli |
| 2004 | Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. | Ajay Kumar Verma, Paolo Ienne |
| 2004 | Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines. | Ranga Vemuri, Glenn Wolfe |
| 2004 | A yield improvement methodology using pre- and post-silicon statistical clock scheduling. | Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja |
| 2004 | Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth. | Maxim Teslenko, Elena Dubrova |
| 2004 | SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits. | Yangfeng Su, Jian Wang, Xuan Zeng, Zhaojun Bai, Charles C. Chiang, Dian Zhou |
| 2004 | Architectural-level synthesis of digital microfluidics-based biochips. | Fei Su, Krishnendu Chakrabarty |
| 2004 | Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing. | Guido Stehr, Helmut E. Graeb, Kurt Antreich |
| 2004 | A general framework for probabilistic low-power design space exploration considering process variation. | Ashish Srivastava, Dennis Sylvester |
| 2004 | Improving soft-error tolerance of FPGA configuration bits. | Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin |
| 2004 | Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. | Debjit Sinha, Hai Zhou |
| 2004 | SPIN-TEST: automatic test pattern generation for speed-independent circuits. | Feng Shi, Yiorgos Makris |
| 2004 | Exploiting level sensitive latches in wire pipelining. | V. Seth, Min Zhao, Jiang Hu |
| 2004 | The impact of device parameter variations on the frequency and performance of VLSI chips. | S. B. Samaan |
| 2004 | Static statistical timing analysis for latch-based pipeline designs. | Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu |