| 2005 | Eliminating wire crossings for molecular quantum-dot cellular automata implementation. | Amitabh Chaudhary, Danny Z. Chen, Kevin Whitton, Michael T. Niemier, Ramprasad Ravichandran |
| 2005 | Reducing structural bias in technology mapping. | Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam |
| 2005 | Response shaper: a novel technique to enhance unknown tolerance for output response compaction. | Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng |
| 2005 | NoCEE: energy macro-model extraction methodology for network on chip routers. | Jeremy Chan, Sri Parameswaran |
| 2005 | Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
| 2005 | Simulation-based bug trace minimization with BMC-based refinement. | Kai-Hui Chang, Valeria Bertacco, Igor L. Markov |
| 2005 | CDMA/FDMA-interconnects for future ULSI communications. | M. Frank Chang |
| 2005 | A cocktail approach on random access scan toward low power and high efficiency test. | Krishnendu Chakrabarty, J. E. Chen |
| 2005 | A statistical study of the effectiveness of BIST jitter measurement techniques. | David Bordoley, Hieu Nguyen, Mani Soma |
| 2005 | Parameterized model order reduction of nonlinear dynamical systems. | Bradley N. Bond, Luca Daniel |
| 2005 | A multi-harmonic probe technique for computing oscillator steady states. | Kapil D. Boianapally, Ting Mei, Jaijeet S. Roychowdhury |
| 2005 | Automatic generalized phase abstraction for formal verification. | Per Bjesse, James H. Kukula |
| 2005 | Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. | Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
| 2005 | Efficient analog platform characterization through analog constraint graphs. | Fernando De Bernardinis, Alberto L. Sangiovanni-Vincentelli |
| 2005 | Pessimism reduction in crosstalk noise aware STA. | Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Amir Grinshpon, Ilan Algor, Rafi Levy, Chanhee Oh |
| 2005 | Complementary use of runtime validation and model checking. | Ali Alphan Bayazit, Sharad Malik |
| 2005 | Efficient LTL compilation for SAT-based model checking. | Roy Armoni, Sergey Egorov, Ranan Fraer, Dmitry Korchemny, Moshe Y. Vardi |
| 2005 | Post-verification debugging of hierarchical designs. | Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler |
| 2005 | An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems. | Ankur Agiwal, Montek Singh |
| 2005 | Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. | Anuradha Agarwal, Ranga Vemuri |
| 2005 | Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations. | Amit Agarwal, Kunhyuk Kang, Kaushik Roy |
| 2005 | Parametric test development for RF circuits targeting physical fault locations and using specification-based fault definitions. | Erkan Acar, Sule Ozev |
| 2004 | Process and environmental variation impacts on ASIC timing. | Paul S. Zuchowski, Peter A. Habitz, J. D. Hayes, J. H. Oppold |
| 2004 | A stochastic integral equation method for modeling the rough surface effect on interconnect capacitance. | Zhenhai Zhu, Jacob K. White, Alper Demir |
| 2004 | The effects of energy management on reliability in real-time embedded systems. | Dakai Zhu, Rami G. Melhem, Daniel Moss |