| 2004 | Efficient full-chip thermal modeling and analysis. | Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra |
| 2004 | Efficient harmonic balance simulation using multi-level frequency decomposition. | Peng Li, Lawrence T. Pileggi |
| 2004 | Optimal wire retiming without binary search. | Chuan Lin, Hai Zhou |
| 2004 | Vdd programmability to reduce FPGA interconnect power. | Fei Li, Yan Lin, Lei He |
| 2004 | Asymptotic probability extraction for non-normal distributions of circuit performance. | Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi |
| 2004 | Robust analog/RF circuit design with projection-based posynomial modeling. | Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi |
| 2004 | Hybrid techniques for electrostatic analysis of nanowires. | Gang Li, Narayan R. Aluru |
| 2004 | A path-based methodology for post-silicon timing validation. | Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng |
| 2004 | SILENT: serialized low energy transmission coding for on-chip interconnection networks. | Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo |
| 2004 | Backend CAD flows for "restrictive design rules". | Mark A. Lavin, Fook-Luen Heng, Gregory A. Northrop |
| 2004 | Automated oscillator macromodelling techniques for capturing amplitude variations and injection locking. | Xiaolue Lai, Jaijeet S. Roychowdhury |
| 2004 | Dynamic transition relation simplification for bounded property checking. | Andreas Kuehlmann |
| 2004 | Checking consistency of C and Verilog using predicate abstraction and induction. | Daniel Kroening, Edmund M. Clarke |
| 2004 | Design/process learning from electrical test. | Bernd Koenemann |
| 2004 | Techniques for improving the accuracy of geometric-programming based analog circuit design optimization. | Jintae Kim, Jaeseo Lee, Lieven Vandenberghe |
| 2004 | Automatic translation of behavioral testbench for fully accelerated simulation. | Young-Il Kim, Chong-Min Kyung |
| 2004 | Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints. | Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna |
| 2004 | Leakage control through fine-grained placement and sizing of sleep transistors. | Vishal Khandelwal, Ankur Srivastava |
| 2004 | Efficient statistical timing analysis through error budgeting. | Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava |
| 2004 | A robust cell-level crosstalk delay change analysis. | Igor Keller, Ken Tseng, Nishath K. Verghese |
| 2004 | Analytical modeling of crosstalk noise waveforms using Weibull function. | Alireza Kasnavi, Joddy W. Wang, Mahmoud Shahram, Jindrich Zejda |
| 2004 | Logical effort based technology mapping. | Shrirang K. Karandikar, Sachin S. Sapatnekar |
| 2004 | A novel clock distribution and dynamic de-skewing methodology. | Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri |
| 2004 | Banked scratch-pad memory management for reducing leakage energy consumption. | Mahmut T. Kandemir, Mary Jane Irwin, Guilin Chen, Ibrahim Kolcu |
| 2004 | An analytic placer for mixed-size placement and timing-driven placement. | Andrew B. Kahng, Qinke Wang |