| 2004 | Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems. | Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi |
| 2004 | Low-power programmable routing circuitry for FPGAs. | Jason Helge Anderson, Farid N. Najm |
| 2004 | Modeling unbuffered latches for timing analysis. | Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail |
| 2004 | Accurate estimation of global buffer delay within a floorplan. | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze |
| 2004 | Debugging sequential circuits using Boolean satisfiability. | Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir |
| 2004 | M-trie: an efficient approach to on-chip logic minimization. | Seraj Ahmad, Rabi N. Mahapatra |
| 2004 | Unification of partitioning, placement and floorplanning. | Saurabh N. Adya, S. Chaturvedi, Jarrod A. Roy, David A. Papa, Igor L. Markov |
| 2003 | Generator-based Verification. | Yunshan Zhu, James H. Kukula |
| 2003 | Gradual Relaxation Techniques with Applications to Behavioral Synthesis. | Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason Cong |
| 2003 | Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems. | Ying Zhang, Krishnendu Chakrabarty, Vishnu Swaminathan |
| 2003 | A Framework for Constrained Functional Verification. | Jun Yuan, Carl Pixley, Adnan Aziz, Ken Albin |
| 2003 | Passive Synthesis of Compact Frequency-Dependent Interconnect Models via Quadrature Spectral Rules. | Traianos V. Yioultsis, Anne Woo, Andreas C. Cangellaris |
| 2003 | Minimum-Area Sequential Budgeting for FPGA. | Chao-Yang Yeh, Malgorzata Marek-Sadowska |
| 2003 | Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. | Le Yan, Jiong Luo, Niraj K. Jha |
| 2003 | FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits. | Lei Yang, Chuanjin Richard Shi |
| 2003 | A Trade-off Oriented Placement Tool. | Huaiyu Xu, Maogang Wang, Bo-Kyung Choi, Majid Sarrafzadeh |
| 2003 | Bus-Driven Floorplanning. | Hua Xiang, Xiaoping Tang, Martin D. F. Wong |
| 2003 | Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints. | Yu Xia, Malgorzata Chrzanowska-Jeske, Benyi Wang, Marcin Jeske |
| 2003 | Multi-Million Gate FPGA Physical Design Challenges. | Maogang Wang, Abhishek Ranjan, Salil Raje |
| 2003 | On Compacting Test Response Data Containing Unknown Values. | Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer |
| 2003 | RTL Power Optimization with Gate-Level Accuracy. | Qi Wang, Sumit Roy |
| 2003 | Improving Ariadnes Bundle by Following Multiple Threads in Abstraction Refinement. | Chao Wang, Bing Li, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi |
| 2003 | The Compositional Far Side of Image Computation. | Chao Wang, Gary D. Hachtel, Fabio Somenzi |
| 2003 | Efficient Iterative Time Preconditioners for Harmonic Balance RF Circuit Simulation. | Fabrice Veers |
| 2003 | Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization. | Girish Varatkar, Radu Marculescu |