| 2004 | Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals. | Peter Feldmann, Frank Liu |
| 2004 | Voltage-drop-constrained optimization of power distribution network based on reliable maximum current estimates. | Nestoras E. Evmorfopoulos, Dimitris P. Karampatzakis, Georgios I. Stamoulis |
| 2004 | Guiding CNF-SAT search via efficient constraint partitioning. | Vijay Durairaj, Priyank Kalla |
| 2004 | Frequency domain simulation of high-Q oscillators with homotopy methods. | Xiaochun Duan, Kartikeya Mayaram |
| 2004 | Variability inspired implementation selection problem. | Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava |
| 2004 | Formal verification coverage: computing the coverage gap between temporal specifications. | Sayantan Das, Prasenjit Basu, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni |
| 2004 | A thermal-driven floorplanning algorithm for 3D ICs. | Jason Cong, Jie Wei, Yan Zhang |
| 2004 | FLUTE: fast lookup table based wirelength estimation technique. | Chris Chu |
| 2004 | Dynamic voltage and frequency scaling under a precise energy model considering variable and fixed components of the system power dissipation. | Kihwan Choi, Wonbok Lee, Ramakrishna Soma, Massoud Pedram |
| 2004 | Minimizing the number of test configurations for FPGAs. | Erik Chmelar |
| 2004 | Fast flip-chip power grid analysis via locality and grid shells. | Eli Chiprout |
| 2004 | A quantitative study and estimation models for extensible instructions in embedded processors. | Newton Cheung, Sri Parameswaran, Jrg Henkel |
| 2004 | Clock schedule verification under process variations. | Ruiming Chen, Hai Zhou |
| 2004 | Timing macro-modeling of IP blocks with crosstalk. | Ruiming Chen, Hai Zhou |
| 2004 | HiSIM: hierarchical interconnect-centric circuit simulator. | Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik |
| 2004 | Floorplan design for multi-million gate FPGAs. | Lei Cheng, Martin D. F. Wong |
| 2004 | DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs. | Deming Chen, Jason Cong |
| 2004 | A new incremental placement algorithm and its application to congestion-aware divisor extraction. | Satrajit Chatterjee, Robert K. Brayton |
| 2004 | A power aware system level interconnect design methodology for latency-insensitive systems. | Vikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi |
| 2004 | Verifying properties of hardware and software by predicate abstraction and model checking. | Randal E. Bryant, Sriram K. Rajamani |
| 2004 | DAG-aware circuit compression for formal verification. | Per Bjesse, Arne Borlv |
| 2004 | How to bridge the abstraction gap in system level modeling and design. | A. Bernstein, M. Burton, Frank Ghenassia |
| 2004 | Design space exploration for a UMTS front-end exploiting analog platforms. | F. De Bernarclinis, S. Gambini, R. Vincis, Francesco Svelto |
| 2004 | High-level synthesis: an essential ingredient for designing complex ASICs. | Arvind, Rishiyur S. Nikhil, Daniel L. Rosenband, Nirav Dave |
| 2004 | Design space exploration for aggressive test cost reduction in CircularScan architectures. | Baris Arslan, Alex Orailoglu |