| 2003 | FAME: A Fault-Pattern Based Memory Failure Analysis Framework. | Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu |
| 2003 | The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. | Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao |
| 2003 | Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal. | Hongliang Chang, Sachin S. Sapatnekar |
| 2003 | An Enhanced Multilevel Algorithm for Circuit Placement. | Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shinnerl, Kenton Sze |
| 2003 | ILP Models for the Synthesis of Asynchronous Control Circuits. | Josep Carmona, Jordi Cortadella |
| 2003 | Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis. | Yu Cao, Xiaodong Yang, Xuejue Huang, Dennis Sylvester |
| 2003 | AU: Timing Analysis Under Uncertainty. | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw |
| 2003 | System Level Design and Verification Using a Synchronous Language. | Grard Berry, Michael Kishinevsky, Satnam Singh |
| 2003 | Design and CAD Challenges in sub-90nm CMOS Technologies. | Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri |
| 2003 | Performance Efficiency of Context-Flow System-on-Chip Platform. | Rami Beidas, Jianwen Zhu |
| 2003 | A Probabilistic-Based Design Methodology for Nanoscale Computation. | R. Iris Bahar, Joseph L. Mundy, Jie Chen |
| 2003 | Weibull Based Analytical Waveform Model. | Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail |
| 2003 | Timing Analysis in Presence of Power Supply and Ground Voltage Variations. | Rubil Ahmadi, Farid N. Najm |
| 2003 | Fractional Cut: Improved Recursive Bisection Placement. | Ameya R. Agnihotri, Mehmet Can Yildiz, Ateen Khatkhate, Ajita Mathur, Satoshi Ono, Patrick H. Madden |
| 2003 | Statistical Clock Skew Analysis Considering Intra-Die Process Variations. | Aseem Agarwal, David T. Blaauw, Vladimir Zolotov |
| 2003 | Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. | Aseem Agarwal, David T. Blaauw, Vladimir Zolotov |
| 2003 | On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis. | Saurabh N. Adya, Igor L. Markov, Paul Villarrubia |
| 2003 | Placement Method Targeting Predictability Robustness and Performance. | Cristinel Ababei, Kia Bazargan |
| 2002 | A hybrid ASIC and FPGA architecture. | Paul S. Zuchowski, Christopher B. Reynolds, Richard J. Grupp, Shelly G. Davis, Brendan Cremen, Bill Troxel |
| 2002 | Noise propagation and failure criteria for VLSI designs. | Vladimir Zolotov, David T. Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy |
| 2002 | A Case for CMOS/nano co-design. | Matthew M. Ziegler, Mircea R. Stan |
| 2002 | A hierarchical modeling framework for on-chip communication architectures. | Xinping Zhu, Sharad Malik |
| 2002 | Symbolic pointer analysis. | Jianwen Zhu |
| 2002 | On-chip interconnect modeling by wire duplication. | Guoan Zhong, Cheng-Kok Koh, Kaushik Roy |
| 2002 | Interconnect-aware high-level synthesis for low power. | Lin Zhong, Niraj K. Jha |