| 2002 | Reversible logic circuit synthesis. | Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes |
| 2002 | Shaping interconnect for uniform current density. | Muzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao |
| 2002 | Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects. | Harshit K. Shah, Pun H. Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis |
| 2002 | Theoretical and practical validation of combined BEM/FEM substrate resistance modeling. | Eelco Schrik, Patrick M. Dewilde, N. P. van der Meijs |
| 2002 | Minimizing power across multiple technology and design levels. | Takayasu Sakurai |
| 2002 | Making Fourier-envelope simulation robust. | Jaijeet S. Roychowdhury |
| 2002 | Battery-aware power management based on Markovian decision processes. | Peng Rong, Massoud Pedram |
| 2002 | Test-model based hierarchical DFT synthesis. | Sanjay Ramnath, Frederic Neuveux, Mokhtar Hirech, Felix Ng |
| 2002 | Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. | Katarzyna Radecka, Zeljko Zilic |
| 2002 | On undetectable faults in partial scan circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2002 | Convertibility verification and converter synthesis: two faces of the same coin. | Roberto Passerone, Luca de Alfaro, Thomas A. Henzinger, Alberto L. Sangiovanni-Vincentelli |
| 2002 | An energy-conscious algorithm for memory port allocation. | Preeti Ranjan Panda, Lakshmikantam Chitturi |
| 2002 | A local circuit topology for inductive parasitics. | Andrea Pacelli |
| 2002 | Fast seed computation for reseeding shift register in test pattern compression. | Nahmsuk Oh, Rohit Kapur, Thomas W. Williams |
| 2002 | High capacity and automatic functional extraction tool for industrial VLSI circuit designs. | Sasha Novakovsky, Shy Shyman, Ziyad Hanna |
| 2002 | Bit-level scheduling of heterogeneous behavioural specifications. | Mara C. Molina, Jos M. Mendas, Romn Hermida |
| 2002 | A realistic variable voltage scheduling model for real-time applications. | Bren Mochocki, Xiaobo Sharon Hu, Gang Quan |
| 2002 | Whirlpool PLAs: a regular logic structure and their synthesis. | Fan Mo, Robert K. Brayton |
| 2002 | Simplification of non-deterministic multi-valued networks. | Alan Mishchenko, Robert K. Brayton |
| 2002 | WTA: waveform-based timing analysis for deep submicron circuits. | Larry McMurchie, Carl Sechen |
| 2002 | FastMag: a 3-D magnetostatic inductance extraction program for structures with permeable materials. | Yehia Massoud, Jacob White |
| 2002 | Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. | Steven M. Martin, Krisztin Flautner, Trevor N. Mudge, David T. Blaauw |
| 2002 | Schedulability analysis of multiprocessor real-time applications with stochastic task execution times. | Sorin Manolache, Petru Eles, Zebo Peng |
| 2002 | Coupling-aware high-level interconnect synthesis for low power. | Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim |
| 2002 | A Markov chain sequence generator for power macromodeling. | Xun Liu, Marios C. Papaefthymiou |